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Searched refs:MIPS_SPL_0_1_2_3 (Results 1 – 4 of 4) sorted by relevance

/netbsd/src/sys/arch/emips/emips/
Dxs_bee3.c69 splvec.splclock = MIPS_SPL_0_1_2_3; //0x3f00
70 splvec.splstatclock = MIPS_SPL_0_1_2_3; //0x3f00
Dxilinx_ml40x.c71 splvec.splclock = MIPS_SPL_0_1_2_3; //0x3f00
72 splvec.splstatclock = MIPS_SPL_0_1_2_3; //0x3f00
/netbsd/src/sys/arch/emips/include/
Dintr.h56 #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2)
/netbsd/src/sys/arch/pmax/include/
Dintr.h51 #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2) macro