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Searched refs:MIPS_COP_0_STATUS (Results 1 – 24 of 24) sorted by relevance

/netbsd/src/sys/arch/mips/mips/
Dspl.S86 mtc0 v1, MIPS_COP_0_STATUS # disable interrupts
88 mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
96 mtc0 a0, MIPS_COP_0_STATUS # store back
104 mfc0 v1, MIPS_COP_0_STATUS
136 mfc0 v1, MIPS_COP_0_STATUS # fetch status register
143 mtc0 v0, MIPS_COP_0_STATUS # disable interrupts
145 mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
149 mtc0 v1, MIPS_COP_0_STATUS # store back
161 mfc0 v1, MIPS_COP_0_STATUS
177 mfc0 a0, MIPS_COP_0_STATUS
[all …]
Dcache_r3k_subr.S71 mfc0 v1, MIPS_COP_0_STATUS
73 mtc0 a0, MIPS_COP_0_STATUS # disable interrupts,
107 mtc0 v1, MIPS_COP_0_STATUS
150 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
151 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
161 mtc0 v1, MIPS_COP_0_STATUS
174 mtc0 t0, MIPS_COP_0_STATUS # Restore SR.
192 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
193 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
198 mtc0 v1, MIPS_COP_0_STATUS
[all …]
Dcache_tx39_subr.S55 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
57 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
84 mtc0 t0, MIPS_COP_0_STATUS # Restore SR.
102 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
104 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
131 mtc0 t0, MIPS_COP_0_STATUS # Restore SR.
Dlocore.S75 mfc0 k0, MIPS_COP_0_STATUS
79 mtc0 k0, MIPS_COP_0_STATUS
85 mtc0 k0, MIPS_COP_0_STATUS
91 mfc0 k0, MIPS_COP_0_STATUS
94 mtc0 k0, MIPS_COP_0_STATUS
96 mfc0 k0, MIPS_COP_0_STATUS
99 mtc0 k0, MIPS_COP_0_STATUS
159 mfc0 k0, MIPS_COP_0_STATUS
162 mtc0 k0, MIPS_COP_0_STATUS
169 mtc0 k0, MIPS_COP_0_STATUS
[all …]
Dlocore_mips3.S176 mfc0 v0, MIPS_COP_0_STATUS
199 mfc0 v0, MIPS_COP_0_STATUS
591 mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts
593 mtc0 t1, MIPS_COP_0_STATUS
607 mtc0 t0, MIPS_COP_0_STATUS # restore intr status.
620 mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts
622 mtc0 t1, MIPS_COP_0_STATUS
637 mtc0 t0, MIPS_COP_0_STATUS # restore intr status.
656 mfc0 t0, MIPS_COP_0_STATUS
660 mtc0 t1, MIPS_COP_0_STATUS
[all …]
Dlocore_mips1.S143 mfc0 k0, MIPS_COP_0_STATUS #00: get the status register
180 mfc0 k0, MIPS_COP_0_STATUS
238 mfc0 a0, MIPS_COP_0_STATUS # 1st arg is STATUS
309 mtc0 a0, MIPS_COP_0_STATUS # restore the SR, disable intrs
441 mfc0 s1, MIPS_COP_0_STATUS
509 mfc0 v1, MIPS_COP_0_STATUS
512 mtc0 v0, MIPS_COP_0_STATUS # write new status
526 mfc0 t0, MIPS_COP_0_STATUS # verify INT_IE is still set
566 mtc0 s1, MIPS_COP_0_STATUS # disable interrupts
588 mfc0 v0, MIPS_COP_0_STATUS
[all …]
Dmips_fpu.c116 "n"(MIPS_COP_0_STATUS)); in mips_fpu_state_save()
206 __asm volatile ("mtc0 %0, $%1" :: "r"(status), "n"(MIPS_COP_0_STATUS)); in mips_fpu_state_save()
246 …_regs[_R_SR] & (MIPS_SR_COP_1_BIT|MIPS3_SR_FR|MIPS_SR_KX|MIPS_SR_INT_IE)), "n"(MIPS_COP_0_STATUS)); in mips_fpu_state_load()
352 "n"(MIPS_COP_0_STATUS)); in mips_fpu_state_load()
DmipsX_subr.S152 mtc0 zero, MIPS_COP_0_STATUS
154 li reg, MIPS_SR_EXL; mtc0 reg, MIPS_COP_0_STATUS
157 li reg, MIPS_SR_KX; mtc0 reg, MIPS_COP_0_STATUS
159 li reg, MIPS_SR_EXL | MIPS_SR_KX; mtc0 reg, MIPS_COP_0_STATUS
617 mfc0 k0, MIPS_COP_0_STATUS #00: get the status register
657 mfc0 k0, MIPS_COP_0_STATUS #00: get the status register
685 mfc0 k0, MIPS_COP_0_STATUS
741 mfc0 a0, MIPS_COP_0_STATUS # 1st arg is STATUS
817 mtc0 v0, MIPS_COP_0_STATUS # update.
841 mtc0 a0, MIPS_COP_0_STATUS # restore the SR, disable intrs
[all …]
Dmips_dsp.c131 [cp0_status] "n"(MIPS_COP_0_STATUS)); in mips_dsp_state_save()
189 [cp0_status] "n"(MIPS_COP_0_STATUS)); in mips_dsp_state_load()
Dlocore_octeon.S163 mfc0 k0, MIPS_COP_0_STATUS # get cp0 status
166 mtc0 k0, MIPS_COP_0_STATUS # write cp0 status
Ddb_disasm.c639 if (i.RType.rd == MIPS_COP_0_STATUS in db_disasm_insn()
Ddb_interface.c474 SHOW32(MIPS_COP_0_STATUS, "status"); in db_cp0dump_cmd()
/netbsd/src/sys/arch/newsmips/stand/boot/
Dlocore.S68 mfc0 v0, MIPS_COP_0_STATUS # save SR
69 mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
77 mtc0 v1, MIPS_COP_0_STATUS
85 mtc0 v0, MIPS_COP_0_STATUS # enable interrupts
/netbsd/src/sys/arch/sgimips/sgimips/
Dip22_cache.S49 mfc0 t0, MIPS_COP_0_STATUS ; \
56 mtc0 t1, MIPS_COP_0_STATUS ; \
63 mtc0 t0, MIPS_COP_0_STATUS ; \
/netbsd/src/sys/arch/mips/rmi/
Drmixl_spl.S86 mfc0 t0, MIPS_COP_0_STATUS # get STATUS
88 mtc0 zero, MIPS_COP_0_STATUS ## disable all ints in STATUS
94 mtc0 t0, MIPS_COP_0_STATUS ## set STATUS | IE
Drmixl_subr.S104 mfc0 t0, MIPS_COP_0_STATUS
119 mtc0 t0, MIPS_COP_0_STATUS
146 mtc0 t0, MIPS_COP_0_STATUS
Drmixl_fmnvar.h205 : "n"(MIPS_COP_0_STATUS), "n"(1 << 30)); in rmixl_cp2_enable()
226 : "n"(MIPS_COP_0_STATUS), "r"(mask), "r"(ocu)); in rmixl_cp2_restore()
/netbsd/src/sys/arch/mipsco/mipsco/
Dlocore_machdep.S45 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
47 mtc0 v0, MIPS_COP_0_STATUS # boot strap exception vector
/netbsd/src/sys/arch/hpcmips/vr/
Dvrip_spl.S64 mfc0 v0, MIPS_COP_0_STATUS # fetch status register
69 mtc0 v0, MIPS_COP_0_STATUS # store back
/netbsd/src/sys/arch/emips/stand/common/
Dstart.S151 mfc0 a0, MIPS_COP_0_STATUS
206 mtc0 k1, MIPS_COP_0_STATUS
317 mtc0 t0,MIPS_COP_0_STATUS
346 mfc0 v0, MIPS_COP_0_STATUS
355 mtc0 a0,MIPS_COP_0_STATUS
/netbsd/src/sys/arch/pmax/pmax/
Dlocore_machdep.S148 mfc0 v0, MIPS_COP_0_STATUS # save original SR in v0
152 mtc0 v1, MIPS_COP_0_STATUS
160 mtc0 v0, MIPS_COP_0_STATUS # restore SR on exit
/netbsd/src/sys/arch/newsmips/newsmips/
Dlocore_machdep.S69 mtc0 v0, MIPS_COP_0_STATUS # boot strap exception vector
/netbsd/src/sys/arch/playstation2/playstation2/
Dlocore_machdep.S111 mtc0 t0, MIPS_COP_0_STATUS
/netbsd/src/sys/arch/mips/include/
Dcpuregs.h583 #define MIPS_COP_0_STATUS _(12) macro