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Searched refs:IO_ICU2 (Results 1 – 22 of 22) sorted by relevance

/netbsd/src/sys/arch/powerpc/pic/
Di8259_common.c57 isa_outb(IO_ICU2, 0x11); /* program device, four bytes */ in i8259_initialize()
58 isa_outb(IO_ICU2+1, 8); /* starting at this vector */ in i8259_initialize()
59 isa_outb(IO_ICU2+1, IRQ_SLAVE); in i8259_initialize()
60 isa_outb(IO_ICU2+1, 1); /* 8086 mode */ in i8259_initialize()
61 isa_outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ in i8259_initialize()
75 isa_outb(IO_ICU2+1, i8259->enable_mask >> 8); in i8259_enable_irq()
86 isa_outb(IO_ICU2+1, i8259->enable_mask >> 8); in i8259_disable_irq()
95 isa_outb(IO_ICU2, 0xe0 | (irq & 7)); in i8259_ack_irq()
108 isa_outb(IO_ICU2, 0x0c); in i8259_get_irq()
109 irq = (isa_inb(IO_ICU2) & 0x07) + 8; in i8259_get_irq()
/netbsd/src/sys/arch/x86/x86/
Di8259.c167 outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_LTIM | ICW1_IC4); in i8259_default_setup()
171 outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); in i8259_default_setup()
174 outb(IO_ICU2 + PIC_ICW2, ICU_OFFSET + 8); in i8259_default_setup()
176 outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE)); in i8259_default_setup()
179 outb(IO_ICU2 + PIC_ICW4, ICW4_AEOI | ICW4_8086); in i8259_default_setup()
182 outb(IO_ICU2 + PIC_ICW4, ICW4_8086); in i8259_default_setup()
185 outb(IO_ICU2 + PIC_OCW1, 0xff); in i8259_default_setup()
187 outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); in i8259_default_setup()
189 outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_RR); in i8259_default_setup()
203 port = IO_ICU2 + PIC_OCW1; in i8259_hwmask()
[all …]
/netbsd/src/sys/arch/ofppc/isa/
Disa_machdep.c66 err = bus_space_map(&genppc_isa_io_space_tag, IO_ICU2, 2, 0, in map_isa_ioregs()
85 if (addr == IO_ICU2 || addr == IO_ICU2+1) in isa_inb()
87 addr-IO_ICU2); in isa_inb()
100 if (addr == IO_ICU2 || addr == IO_ICU2+1) in isa_outb()
102 addr-IO_ICU2, val); in isa_outb()
/netbsd/src/sys/arch/shark/isa/
Disa_shark_machdep.c132 outb(IO_ICU2, 0x19); /* reset; four bytes, level triggered */ in isa_init8259s()
133 outb(IO_ICU2+1, ICU_OFFSET+8); /* int base + offset for master: not used */ in isa_init8259s()
134 outb(IO_ICU2+1, IRQ_SLAVE); /* who ami i? */ in isa_init8259s()
135 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ in isa_init8259s()
136 outb(IO_ICU2+1, 0xff); /* disable all interrupts */ in isa_init8259s()
137 outb(IO_ICU2, 0x68); /* special mask mode (if available) */ in isa_init8259s()
138 outb(IO_ICU2, 0x0a); /* Read IRR by default. */ in isa_init8259s()
Dicu.h54 outb(IO_ICU2 + 1, imen >> 8); \
Disa_irq.S146 ldrbne r1, [r0, #IO_ICU2] /* ocw3 = irr */
370 strbne r1, [r0, #(IO_ICU2 + 1)] /* icu2 / ocw1 */
/netbsd/src/sys/arch/arc/isa/
Disabus.c312 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); in intr_calculatemasks()
428 isa_inb(IO_ICU2 + PIC_OCW1); in isabr_iointr()
429 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); in isabr_iointr()
430 isa_outb(IO_ICU2 + PIC_OCW2, in isabr_iointr()
457 isa_inb(IO_ICU2 + PIC_OCW1); in isabr_iointr()
459 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); in isabr_iointr()
509 isa_outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); in isabr_initicu()
511 isa_outb(IO_ICU2 + PIC_ICW2, 8); in isabr_initicu()
513 isa_outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE)); in isabr_initicu()
515 isa_outb(IO_ICU2 + PIC_ICW4, ICW4_8086); in isabr_initicu()
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/netbsd/src/sys/arch/evbmips/loongson/
Dyeeloong_machdep.c301 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff; in lemote_pci_attach_hook()
302 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW1) = in lemote_pci_attach_hook()
304 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW2) = ICW2_VECTOR(8); in lemote_pci_attach_hook()
305 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW3) = ICW3_SIC(2); in lemote_pci_attach_hook()
306 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW4) = ICW4_8086; in lemote_pci_attach_hook()
309 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff; in lemote_pci_attach_hook()
311 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = OCW3_SELECT | OCW3_RR; in lemote_pci_attach_hook()
312 (void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3); in lemote_pci_attach_hook()
485 imr2 = 0xff & ~REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1); in lemote_get_isa_imr()
497 isr2 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU2); in lemote_get_isa_isr()
Disa_machdep.c62 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) = imr2; in loongson_set_isa_imr()
75 (void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1); in loongson_isa_specific_eoi()
76 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) = in loongson_isa_specific_eoi()
79 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW2) = in loongson_isa_specific_eoi()
Dgeneric2e_machdep.c305 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = in generic2e_isa_intr()
307 ocw2 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3); in generic2e_isa_intr()
577 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW1) = in via686sb_setup()
579 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW2) = ICW2_VECTOR(8); in via686sb_setup()
580 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW3) = ICW3_SIC(2); in via686sb_setup()
581 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW4) = ICW4_8086; in via686sb_setup()
583 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff; in via686sb_setup()
585 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = in via686sb_setup()
588 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = OCW3_SELECT | OCW3_RR; in via686sb_setup()
/netbsd/src/sys/arch/arm/footbridge/isa/
Disa_machdep.c140 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ in isa_icu_init()
141 outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */ in isa_icu_init()
142 outb(IO_ICU2+1, IRQ_SLAVE); in isa_icu_init()
144 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ in isa_icu_init()
146 outb(IO_ICU2+1, 1); /* 8086 mode */ in isa_icu_init()
148 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ in isa_icu_init()
149 outb(IO_ICU2, 0x68); /* special mask mode (if available) */ in isa_icu_init()
150 outb(IO_ICU2, 0x0a); /* Read IRR by default. */ in isa_icu_init()
Dicu.h54 outb(IO_ICU2 + 1, imen >> 8); \
/netbsd/src/sys/arch/arc/arc/
Dc_isa.c188 isa_outb(IO_ICU2, 0x0f); in isabr_dti_intr_status()
189 vector = isa_inb(IO_ICU2); in isabr_dti_intr_status()
/netbsd/src/sys/arch/x86/include/
Di8259.h50 #define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
111 outb %al,$IO_ICU2 /* do the second ICU first */ ;\
/netbsd/src/sys/dev/isa/
Disareg.h59 #define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ macro
/netbsd/src/sys/arch/alpha/jensenio/
Djensenio_intr.c375 static const int picaddr[2] = { IO_ICU1, IO_ICU2 }; in jensenio_pic_init()
/netbsd/src/sys/arch/cobalt/cobalt/
Dinterrupt.c179 bus_space_map(icu_bst, PCIB_BASE + IO_ICU2, IO_ICUSIZE, 0, &icu2_bsh); in intr_init()
/netbsd/src/sys/arch/alpha/pci/
Dsio_pic.c348 bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2)) in sio_intr_setup()
/netbsd/src/sys/arch/algor/pci/
Dpcib.c170 if (bus_space_map(sc->sc_iot, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0) in pcib_attach()
/netbsd/src/sys/arch/evbmips/malta/pci/
Dpcib.c212 if (bus_space_map(sc->sc_iot, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0) in pcib_attach()
/netbsd/src/sys/arch/amd64/amd64/
Dvector.S466 #define ICUADDR IO_ICU2
/netbsd/src/sys/arch/i386/i386/
Dvector.S479 #define ICUADDR IO_ICU2