1 /* $NetBSD: instr.h,v 1.8 2005/12/11 12:19:05 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)instr.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* see also Appendix F of the SPARC version 8 document */ 44 enum IOP { IOP_OP2, IOP_CALL, IOP_reg, IOP_mem }; 45 enum IOP2 { IOP2_UNIMP, IOP2_BPcc, IOP2_Bicc, IOP2_BPr, 46 IOP2_SETHI, IOP2_FBPfcc, IOP2_FBfcc, IOP2_CBccc }; 47 enum IOP3_reg { 48 IOP3_ADD, IOP3_AND, IOP3_OR, IOP3_XOR, 49 IOP3_SUB, IOP3_ANDN, IOP3_ORN, IOP3_XNOR, 50 IOP3_ADDX, IOP3_rerr09, IOP3_UMUL, IOP3_SMUL, 51 IOP3_SUBX, IOP3_rerr0d, IOP3_UDIV, IOP3_SDIV, 52 IOP3_ADDcc, IOP3_ANDcc, IOP3_ORcc, IOP3_XORcc, 53 IOP3_SUBcc, IOP3_ANDNcc, IOP3_ORNcc, IOP3_XNORcc, 54 IOP3_ADDXcc, IOP3_rerr19, IOP3_UMULcc, IOP3_SMULcc, 55 IOP3_SUBXcc, IOP3_rerr1d, IOP3_UDIVcc, IOP3_SDIVcc, 56 IOP3_TADDcc, IOP3_TSUBcc, IOP3_TADDccTV, IOP3_TSUBccTV, 57 IOP3_MULScc, IOP3_SLL, IOP3_SRL, IOP3_SRA, 58 IOP3_RDASR_RDY_STBAR, IOP3_RDPSR, IOP3_RDWIM, IOP3_RDTGBR, 59 IOP3_rerr2c, IOP3_rerr2d, IOP3_rerr2e, IOP3_rerr2f, 60 IOP3_WRASR_WRY, IOP3_WRPSR, IOP3_WRWIM, IOP3_WRTBR, 61 IOP3_FPop1, IOP3_FPop2, IOP3_CPop1, IOP3_CPop2, 62 IOP3_JMPL, IOP3_RETT, IOP3_Ticc, IOP3_FLUSH, 63 IOP3_SAVE, IOP3_RESTORE, IOP3_rerr3e, IOP3_rerr3f 64 }; 65 enum IOP3_mem { 66 IOP3_LD, IOP3_LDUB, IOP3_LDUH, IOP3_LDD, 67 IOP3_ST, IOP3_STB, IOP3_STH, IOP3_STD, 68 IOP3_merr08, IOP3_LDSB, IOP3_LDSH, IOP3_merr0b, 69 IOP3_merr0c, IOP3_LDSTUB, IOP3_merr0f, IOP3_SWAP, 70 IOP3_LDA, IOP3_LDUBA, IOP3_LDUHA, IOP3_LDDA, 71 IOP3_STA, IOP3_STBA, IOP3_STHA, IOP3_STDA, 72 IOP3_merr18, IOP3_LDSBA, IOP3_LDSHA, IOP3_merr1b, 73 IOP3_merr1c, IOP3_LDSTUBA, IOP3_merr1f, IOP3_SWAPA, 74 IOP3_LDF, IOP3_LDFSR, IOP3_merr22, IOP3_LDDF, 75 IOP3_STF, IOP3_STFSR, IOP3_STDFQ, IOP3_STDF, 76 IOP3_merr28, IOP3_merr29, IOP3_merr2a, IOP3_merr2b, 77 IOP3_merr2c, IOP3_merr2d, IOP3_merr2e, IOP3_merr2f, 78 IOP3_LFC, IOP3_LDCSR, IOP3_merr32, IOP3_LDDC, 79 IOP3_STC, IOP3_STCSR, IOP3_STDCQ, IOP3_STDC, 80 IOP3_merr38, IOP3_merr39, IOP3_merr3a, IOP3_merr3b, 81 IOP3_merr3c, IOP3_merr3d, IOP3_merr3e, IOP3_merr3f 82 }; 83 84 /* 85 * Integer condition codes. 86 */ 87 #define Icc_N 0x0 /* never */ 88 #define Icc_E 0x1 /* equal (equiv. zero) */ 89 #define Icc_LE 0x2 /* less or equal */ 90 #define Icc_L 0x3 /* less */ 91 #define Icc_LEU 0x4 /* less or equal unsigned */ 92 #define Icc_CS 0x5 /* carry set (equiv. less unsigned) */ 93 #define Icc_NEG 0x6 /* negative */ 94 #define Icc_VS 0x7 /* overflow set */ 95 #define Icc_A 0x8 /* always */ 96 #define Icc_NE 0x9 /* not equal (equiv. not zero) */ 97 #define Icc_G 0xa /* greater */ 98 #define Icc_GE 0xb /* greater or equal */ 99 #define Icc_GU 0xc /* greater unsigned */ 100 #define Icc_CC 0xd /* carry clear (equiv. gtr or eq unsigned) */ 101 #define Icc_POS 0xe /* positive */ 102 #define Icc_VC 0xf /* overflow clear */ 103 104 /* 105 * Integer registers. 106 */ 107 #define I_G0 0 108 #define I_G1 1 109 #define I_G2 2 110 #define I_G3 3 111 #define I_G4 4 112 #define I_G5 5 113 #define I_G6 6 114 #define I_G7 7 115 #define I_O0 8 116 #define I_O1 9 117 #define I_O2 10 118 #define I_O3 11 119 #define I_O4 12 120 #define I_O5 13 121 #define I_O6 14 122 #define I_O7 15 123 #define I_L0 16 124 #define I_L1 17 125 #define I_L2 18 126 #define I_L3 19 127 #define I_L4 20 128 #define I_L5 21 129 #define I_L6 22 130 #define I_L7 23 131 #define I_I0 24 132 #define I_I1 25 133 #define I_I2 26 134 #define I_I3 27 135 #define I_I4 28 136 #define I_I5 29 137 #define I_I6 30 138 #define I_I7 31 139 140 /* 141 * An instruction. 142 */ 143 union instr { 144 int i_int; /* as a whole */ 145 146 /* 147 * The first level of decoding is to use the top 2 bits. 148 * This gives us one of three `formats', which usually give 149 * a second level of decoding. 150 */ 151 struct { 152 u_int i_op:2; /* first-level decode */ 153 u_int :30; 154 } i_any; 155 156 /* 157 * Format 1 instructions: CALL (undifferentiated). 158 */ 159 struct { 160 u_int :2; /* 01 */ 161 int i_disp:30; /* displacement */ 162 } i_call; 163 164 /* 165 * Format 2 instructions (SETHI, UNIMP, and branches, plus illegal 166 * unused codes). 167 */ 168 struct { 169 u_int :2; /* 00 */ 170 u_int :5; 171 u_int i_op2:3; /* second-level decode */ 172 u_int :22; 173 } i_op2; 174 175 /* UNIMP, SETHI */ 176 struct { 177 u_int :2; /* 00 */ 178 u_int i_rd:5; /* destination register */ 179 u_int i_op2:3; /* opcode: UNIMP or SETHI */ 180 u_int i_imm:22; /* immediate value */ 181 } i_imm22; 182 183 /* branches: Bicc, FBfcc, CBccc */ 184 struct { 185 u_int :2; /* 00 */ 186 u_int i_annul:1; /* annul bit */ 187 u_int i_cond:4; /* condition codes */ 188 u_int i_op2:3; /* opcode: {Bi,FBf,CBc}cc */ 189 int i_disp:22; /* branch displacement */ 190 } i_branch; 191 192 /* more branches: BPcc, FBPfcc */ 193 struct { 194 u_int :2; /* 00 */ 195 u_int i_annul:1; /* annul bit */ 196 u_int i_cond:4; /* condition codes */ 197 u_int i_op2:3; /* opcode: {BP,FBPf}cc */ 198 u_int i_cc:2; /* condition code selector */ 199 u_int i_pred:1; /* branch prediction bit */ 200 int i_disp:19; /* branch displacement */ 201 } i_branch_p; 202 203 /* one last branch: BPr */ 204 struct { 205 u_int :2; /* 00 */ 206 u_int i_annul:1; /* annul bit */ 207 u_int :1; /* 0 */ 208 u_int i_rcond:4; /* register condition */ 209 u_int :3; /* 011 */ 210 int i_disphi:2; /* branch displacement, hi bits */ 211 u_int i_pred:1; /* branch prediction bit */ 212 u_int i_rs1:1; /* source register 1 */ 213 u_int i_displo:16; /* branch displacement, lo bits */ 214 } i_branch_pr; 215 216 217 /* 218 * Format 3 instructions (memory reference; arithmetic, logical, 219 * shift, and other miscellaneous operations). The second-level 220 * decode almost always makes use of an `rd' and `rs1', however 221 * (see also IOP3_reg and IOP3_mem). 222 * 223 * Beyond that, the low 14 bits may be broken up in one of three 224 * different ways, if at all: 225 * 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem] 226 * 1 bit of imm=1 + 13 bits of signed immediate [reg & mem] 227 * 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only] 228 */ 229 struct { 230 u_int :2; /* 10 or 11 */ 231 u_int i_rd:5; /* destination register */ 232 u_int i_op3:6; /* second-level decode */ 233 u_int i_rs1:5; /* source register 1 */ 234 u_int i_low14:14; /* varies */ 235 } i_op3; 236 237 /* 238 * Memory forms. These set i_op=3 and use simm13 or asi layout. 239 * Memory references without an ASI should use 0, but the actual 240 * ASI field is simply ignored. 241 */ 242 struct { 243 u_int :2; /* 11 only */ 244 u_int i_rd:5; /* destination register */ 245 u_int i_op3:6; /* second-level decode (see IOP3_mem) */ 246 u_int i_rs1:5; /* source register 1 */ 247 u_int i_i:1; /* immediate vs asi */ 248 u_int i_low13:13; /* depend on i bit */ 249 } i_loadstore; 250 251 /* 252 * Memory and register forms. 253 * These come in quite a variety and we do not 254 * attempt to break them down much. 255 */ 256 struct { 257 u_int :2; /* 10 or 11 */ 258 u_int i_rd:5; /* destination register */ 259 u_int i_op3:6; /* second-level decode */ 260 u_int i_rs1:5; /* source register 1 */ 261 u_int i_i:1; /* immediate bit (1) */ 262 int i_simm13:13; /* signed immediate */ 263 } i_simm13; 264 struct { 265 u_int :2; /* 10 or 11 */ 266 u_int i_rd:5; /* destination register */ 267 u_int i_op3:6; /* second-level decode */ 268 u_int i_rs1:5; /* source register 1 */ 269 u_int i_i:1; /* immediate vs asi */ 270 u_int i_asi:8; /* asi */ 271 u_int i_rs2:5; /* source register 2 */ 272 } i_asi; 273 struct { 274 u_int :2; /* 10 only (register, no memory) */ 275 u_int i_rd:5; /* destination register */ 276 u_int i_op3:6; /* second-level decode (see IOP3_reg) */ 277 u_int i_rs1:5; /* source register 1 */ 278 u_int i_opf:9; /* coprocessor 3rd-level decode */ 279 u_int i_rs2:5; /* source register 2 */ 280 } i_opf; 281 282 /* 283 * Format 4 instructions (movcc, fmovr, fmovcc, and tcc). The 284 * second-level decode almost always makes use of an `rd' and either 285 * `rs1' or `cond'. 286 * 287 * Beyond that, the low 14 bits may be broken up in one of three 288 * different ways, if at all: 289 * 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem] 290 * 1 bit of imm=1 + 13 bits of signed immediate [reg & mem] 291 * 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only] */ 292 struct { 293 u_int :2; /* 10 */ 294 u_int i_rd:5; /* destination register */ 295 u_int i_op3:6; /* second-level decode */ 296 u_int i_rs1:5; /* source register 1 */ 297 u_int i_low14:14; /* varies */ 298 } i_op4; 299 300 /* 301 * Move fp register on condition codes. 302 */ 303 struct { 304 u_int :2; /* 10 */ 305 u_int i_rd:5; /* destination register */ 306 u_int i_op3:6; /* second-level decode */ 307 u_int :1; 308 u_int i_cond:4; /* condition */ 309 u_int i_opf_cc:3; /* condition code register */ 310 u_int i_opf_low:6; /* third level decode */ 311 u_int i_rs2:5; /* source register */ 312 } i_fmovcc; 313 314 /* 315 * Move fp register on integer register. 316 */ 317 struct { 318 u_int :2; /* 10 */ 319 u_int i_rd:5; /* destination register */ 320 u_int i_op3:6; /* second-level decode */ 321 u_int i_rs1:5; /* source register 1 */ 322 u_int :1; 323 u_int i_rcond:3; /* register condition */ 324 u_int i_opf_low:6; 325 u_int i_rs2:5; /* source register 2 */ 326 } i_fmovr; 327 328 }; 329 330 /* 331 * Internal macros for building instructions. These correspond 1-to-1 to 332 * the names above. Note that x << y | z == (x << y) | z. 333 */ 334 #define _I_ANY(op, b) ((op) << 30 | (b)) 335 336 #define _I_OP2(high, op2, low) \ 337 _I_ANY(IOP_OP2, (high) << 25 | (op2) << 22 | (low)) 338 #define _I_IMM22(rd, op2, imm) \ 339 _I_ANY(IOP_OP2, (rd) << 25 | (op2) << 22 | (imm)) 340 #define _I_BRANCH(a, c, op2, disp) \ 341 _I_ANY(IOP_OP2, (a) << 29 | (c) << 25 | (op2) << 22 | (disp)) 342 #define _I_FBFCC(a, cond, disp) \ 343 _I_BRANCH(a, cond, IOP2_FBfcc, disp) 344 #define _I_CBCCC(a, cond, disp) \ 345 _I_BRANCH(a, cond, IOP2_CBccc, disp) 346 347 #define _I_SIMM(simm) (1 << 13 | ((simm) & 0x1fff)) 348 349 #define _I_OP3_GEN(form, rd, op3, rs1, low14) \ 350 _I_ANY(form, (rd) << 25 | (op3) << 19 | (rs1) << 14 | (low14)) 351 #define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \ 352 _I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2)) 353 #define _I_OP3_LS_RI(rd, op3, rs1, simm13) \ 354 _I_OP3_GEN(IOP_mem, rd, op3, rs1, _I_SIMM(simm13)) 355 #define _I_OP3_LS_RR(rd, op3, rs1, rs2) \ 356 _I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2) 357 #define _I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \ 358 _I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2)) 359 #define _I_OP3_R_RI(rd, op3, rs1, simm13) \ 360 _I_OP3_GEN(IOP_reg, rd, op3, rs1, _I_SIMM(simm13)) 361 #define _I_OP3_R_RR(rd, op3, rs1, rs2) \ 362 _I_OP3_GEN(IOP_reg, rd, op3, rs1, rs2) 363 364 #define I_CALL(d) _I_ANY(IOP_CALL, d) 365 #define I_UNIMP(v) _I_IMM22(0, IOP2_UNIMP, v) 366 #define I_BN(a, d) _I_BRANCH(a, Icc_N, IOP2_Bicc, d) 367 #define I_BE(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d) 368 #define I_BZ(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d) 369 #define I_BLE(a, d) _I_BRANCH(a, Icc_LE, IOP2_Bicc, d) 370 #define I_BL(a, d) _I_BRANCH(a, Icc_L, IOP2_Bicc, d) 371 #define I_BLEU(a, d) _I_BRANCH(a, Icc_LEU, IOP2_Bicc, d) 372 #define I_BCS(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d) 373 #define I_BLU(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d) 374 #define I_BNEG(a, d) _I_BRANCH(a, Icc_NEG, IOP2_Bicc, d) 375 #define I_BVS(a, d) _I_BRANCH(a, Icc_VS, IOP2_Bicc, d) 376 #define I_BA(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d) 377 #define I_B(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d) 378 #define I_BNE(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d) 379 #define I_BNZ(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d) 380 #define I_BG(a, d) _I_BRANCH(a, Icc_G, IOP2_Bicc, d) 381 #define I_BGE(a, d) _I_BRANCH(a, Icc_GE, IOP2_Bicc, d) 382 #define I_BGU(a, d) _I_BRANCH(a, Icc_GU, IOP2_Bicc, d) 383 #define I_BCC(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d) 384 #define I_BGEU(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d) 385 #define I_BPOS(a, d) _I_BRANCH(a, Icc_POS, IOP2_Bicc, d) 386 #define I_BVC(a, d) _I_BRANCH(a, Icc_VC, IOP2_Bicc, d) 387 #define I_SETHI(r, v) _I_IMM22(r, 4, v) 388 389 #define I_ORri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_OR, rs1, imm) 390 #define I_ORrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_OR, rs1, rs2) 391 392 #define I_MOVi(rd, imm) _I_OP3_R_RI(rd, IOP3_OR, I_G0, imm) 393 #define I_MOVr(rd, rs) _I_OP3_R_RR(rd, IOP3_OR, I_G0, rs) 394 395 #define I_RDPSR(rd) _I_OP3_R_RR(rd, IOP3_RDPSR, 0, 0) 396 397 #define I_JMPLri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_JMPL, rs1, imm) 398 #define I_JMPLrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_JMPL, rs1, rs2) 399 400 /* 401 * (Since these are sparse, we skip the enumerations for now.) 402 * FPop values. All appear in both FPop1 and FPop2 spaces, but arithmetic 403 * ops should happen only with FPop1 and comparison only with FPop2. 404 * The type sits in the low two bits; those bits are given as zero here. 405 */ 406 #define FMOV 0x00 407 #define FNEG 0x04 408 #define FABS 0x08 409 #define FSQRT 0x28 410 #define FADD 0x40 411 #define FSUB 0x44 412 #define FMUL 0x48 413 #define FDIV 0x4c 414 #define FCMP 0x50 415 #define FCMPE 0x54 416 #define FSMULD 0x68 417 #define FDMULX 0x6c 418 #define FTOX 0x80 419 #define FXTOS 0x84 420 #define FXTOD 0x88 421 #define FXTOQ 0x8c 422 #define FTOS 0xc4 423 #define FTOD 0xc8 424 #define FTOQ 0xcc 425 #define FTOI 0xd0 426 427 /* These are in FPop2 space */ 428 #define FMVFC0 0x00 429 #define FMVRZ 0x24 430 #define FMVFC1 0x40 431 #define FMVRLEZ 0x44 432 #define FMVRLZ 0x64 433 #define FMVFC2 0x80 434 #define FMVRNZ 0xa4 435 #define FMVFC3 0xc0 436 #define FMVRGZ 0xc4 437 #define FMVRGEZ 0xe4 438 #define FMVIC 0x100 439 #define FMVXC 0x180 440 441 /* 442 * FPU data types. 443 */ 444 #define FTYPE_LNG -1 /* data = 64-bit signed long integer */ 445 #define FTYPE_INT 0 /* data = 32-bit signed integer */ 446 #define FTYPE_SNG 1 /* data = 32-bit float */ 447 #define FTYPE_DBL 2 /* data = 64-bit double */ 448 #define FTYPE_EXT 3 /* data = 128-bit extended (quad-prec) */ 449