1 /* $Id: imx23_timrotreg.h,v 1.1 2012/11/20 19:06:14 jkunz Exp $ */
2 
3 /*
4  * Copyright (c) 2012 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Petri Laakso.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef _ARM_IMX_IMX23_TIMROTREG_H_
33 #define _ARM_IMX_IMX23_TIMROTREG_H_
34 
35 #include <sys/cdefs.h>
36 
37 #define HW_TIMROT_BASE 0x80068000
38 #define HW_TIMROT_SIZE 0x2000
39 
40 /*
41  * Rotary Decoder Control Register.
42  */
43 #define HW_TIMROT_ROTCTRL     0x000
44 #define HW_TIMROT_ROTCTRL_SET 0x004
45 #define HW_TIMROT_ROTCTRL_CLR 0x008
46 #define HW_TIMROT_ROTCTRL_TOG 0x00C
47 
48 #define HW_TIMROT_ROTCTRL_SFTRST                  __BIT(31)
49 #define HW_TIMROT_ROTCTRL_CLKGATE                 __BIT(30)
50 #define HW_TIMROT_ROTCTRL_ROTARY_PRESENT          __BIT(29)
51 #define HW_TIMROT_ROTCTRL_TIM3_PRESENT            __BIT(28)
52 #define HW_TIMROT_ROTCTRL_TIM2_PRESENT            __BIT(27)
53 #define HW_TIMROT_ROTCTRL_TIM1_PRESENT            __BIT(26)
54 #define HW_TIMROT_ROTCTRL_TIM0_PRESENT            __BIT(25)
55 #define HW_TIMROT_ROTCTRL_STATE                             __BITS(24, 22)
56 #define HW_TIMROT_ROTCTRL_DIVIDER                 __BITS(21, 16)
57 #define HW_TIMROT_ROTCTRL_RSRVD3                  __BITS(15, 13)
58 #define HW_TIMROT_ROTCTRL_RELATIVE                __BIT(12)
59 #define HW_TIMROT_ROTCTRL_OVERSAMPLE              __BITS(11, 10)
60 #define HW_TIMROT_ROTCTRL_POLARITY_B              __BIT(9)
61 #define HW_TIMROT_ROTCTRL_POLARITY_A              __BIT(8)
62 #define HW_TIMROT_ROTCTRL_RSRVD2                  __BIT(7)
63 #define HW_TIMROT_ROTCTRL_SELECT_B                __BITS(6, 4)
64 #define HW_TIMROT_ROTCTRL_RSRVD1                  __BIT(3)
65 #define HW_TIMROT_ROTCTRL_SELECT_A                __BITS(2, 0)
66 
67 /*
68  * Rotary Decoder Up/Down Counter Register.
69  */
70 #define HW_TIMROT_ROTCOUNT 0x010
71 
72 #define HW_TIMROT_ROTCOUNT_RSRVD1       __BITS(31, 16)
73 #define HW_TIMROT_ROTCOUNT_UPDOWN       __BITS(15, 0)
74 
75 /*
76  * Timer 0 Control and Status Register.
77  */
78 #define HW_TIMROT_TIMCTRL0    0x020
79 #define HW_TIMROT_TIMCTRL0_SET          0x024
80 #define HW_TIMROT_TIMCTRL0_CLR          0x028
81 #define HW_TIMROT_TIMCTRL0_TOG          0x02C
82 
83 #define HW_TIMROT_TIMCTRL0_RSRVD2       __BITS(31, 16)
84 #define HW_TIMROT_TIMCTRL0_IRQ                    __BIT(15)
85 #define HW_TIMROT_TIMCTRL0_IRQ_EN       __BIT(14)
86 #define HW_TIMROT_TIMCTRL0_RSRVD1       __BITS(13, 9)
87 #define HW_TIMROT_TIMCTRL0_POLARITY     __BIT(8)
88 #define HW_TIMROT_TIMCTRL0_UPDATE       __BIT(7)
89 #define HW_TIMROT_TIMCTRL0_RELOAD       __BIT(6)
90 #define HW_TIMROT_TIMCTRL0_PRESCALE     __BITS(5, 4)
91 #define HW_TIMROT_TIMCTRL0_SELECT       __BITS(3, 0)
92 
93 /*
94  * Timer 0 Count Register.
95  */
96 #define HW_TIMROT_TIMCOUNT0   0x030
97 
98 #define HW_TIMROT_TIMCOUNT0_RUNNING_COUNT         __BITS(31, 16)
99 #define HW_TIMROT_TIMCOUNT0_FIXED_COUNT           __BITS(15, 0)
100 
101 /*
102  * Timer 1 Control and Status Register.
103  */
104 #define HW_TIMROT_TIMCTRL1    0x040
105 #define HW_TIMROT_TIMCTRL1_SET          0x044
106 #define HW_TIMROT_TIMCTRL1_CLR          0x048
107 #define HW_TIMROT_TIMCTRL1_TOG          0x04C
108 
109 #define HW_TIMROT_TIMCTRL1_RSRVD2       __BITS(31, 16)
110 #define HW_TIMROT_TIMCTRL1_IRQ                    __BIT(15)
111 #define HW_TIMROT_TIMCTRL1_IRQ_EN       __BIT(14)
112 #define HW_TIMROT_TIMCTRL1_RSRVD1       __BITS(13, 9)
113 #define HW_TIMROT_TIMCTRL1_POLARITY     __BIT(8)
114 #define HW_TIMROT_TIMCTRL1_UPDATE       __BIT(7)
115 #define HW_TIMROT_TIMCTRL1_RELOAD       __BIT(6)
116 #define HW_TIMROT_TIMCTRL1_PRESCALE     __BITS(5, 4)
117 #define HW_TIMROT_TIMCTRL1_SELECT       __BITS(3, 0)
118 
119 /*
120  * Timer 1 Count Register.
121  */
122 #define HW_TIMROT_TIMCOUNT1   0x050
123 
124 #define HW_TIMROT_TIMCOUNT1_RUNNING_COUNT         __BITS(31, 16)
125 #define HW_TIMROT_TIMCOUNT1_FIXED_COUNT           __BITS(15, 0)
126 
127 /*
128  * Timer 2 Control and Status Register.
129  */
130 #define HW_TIMROT_TIMCTRL2    0x060
131 #define HW_TIMROT_TIMCTRL2_SET          0x064
132 #define HW_TIMROT_TIMCTRL2_CLR          0x068
133 #define HW_TIMROT_TIMCTRL2_TOG          0x06C
134 
135 #define HW_TIMROT_TIMCTRL2_RSRVD2       __BITS(31, 16)
136 #define HW_TIMROT_TIMCTRL2_IRQ                    __BIT(15)
137 #define HW_TIMROT_TIMCTRL2_IRQ_EN       __BIT(14)
138 #define HW_TIMROT_TIMCTRL2_RSRVD1       __BITS(13, 9)
139 #define HW_TIMROT_TIMCTRL2_POLARITY     __BIT(8)
140 #define HW_TIMROT_TIMCTRL2_UPDATE       __BIT(7)
141 #define HW_TIMROT_TIMCTRL2_RELOAD       __BIT(6)
142 #define HW_TIMROT_TIMCTRL2_PRESCALE     __BITS(5, 4)
143 #define HW_TIMROT_TIMCTRL2_SELECT       __BIT(3, 0)
144 
145 /*
146  * Timer 2 Count Register.
147  */
148 #define HW_TIMROT_TIMCOUNT2   0x070
149 
150 #define HW_TIMROT_TIMCOUNT2_RUNNING_COUNT         __BITS(31, 16)
151 #define HW_TIMROT_TIMCOUNT2_FIXED_COUNT           __BITS(15, 0)
152 
153 /*
154  * Timer 3 Control and Status Register.
155  */
156 #define HW_TIMROT_TIMCTRL3    0x080
157 #define HW_TIMROT_TIMCTRL3_SET          0x084
158 #define HW_TIMROT_TIMCTRL3_CLR          0x088
159 #define HW_TIMROT_TIMCTRL3_TOG          0x08C
160 
161 #define HW_TIMROT_TIMCTRL3_RSRVD2       __BITS(31, 20)
162 #define HW_TIMROT_TIMCTRL3_TEST_SIGNAL  __BITS(19, 16)
163 #define HW_TIMROT_TIMCTRL3_IRQ                    __BIT(15)
164 #define HW_TIMROT_TIMCTRL3_IRQ_EN       __BIT(14)
165 #define HW_TIMROT_TIMCTRL3_RSRVD1       __BITS(13, 11)
166 #define HW_TIMROT_TIMCTRL3_DUTY_VALID   __BIT(10)
167 #define HW_TIMROT_TIMCTRL3_DUTY_CYCLE   __BIT(9)
168 #define HW_TIMROT_TIMCTRL3_POLARITY     __BIT(8)
169 #define HW_TIMROT_TIMCTRL3_UPDATE       __BIT(7)
170 #define HW_TIMROT_TIMCTRL3_RELOAD       __BIT(6)
171 #define HW_TIMROT_TIMCTRL3_PRESCALE     __BITS(5, 4)
172 #define HW_TIMROT_TIMCTRL3_SELECT       __BITS(3, 0)
173 
174 /*
175  * Timer 3 Count Register.
176  */
177 #define HW_TIMROT_TIMCOUNT3   0x090
178 
179 #define HW_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT     __BITS(31, 16)
180 #define HW_TIMROT_TIMCOUNT3IHIGH_FIXED_COUNT      __BITS(15, 0)
181 
182 /*
183  * TIMROT Version Register.
184  */
185 #define HW_TIMROT_VERSION     0x0a0
186 
187 #define HW_TIMROT_VERSION_MAJOR         __BITS(31, 24)
188 #define HW_TIMROT_VERSION_MINOR         __BITS(23, 16)
189 #define HW_TIMROT_VERSION_STEP          __BITS(15, 0)
190 
191 #endif /* !_ARM_IMX_IMX23_TIMROTREG_H_ */
192