1 /* $NetBSD: mvsdioreg.h,v 1.2 2016/03/12 00:41:31 jklos Exp $ */ 2 /* 3 * Copyright (c) 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _MVSDIOREG_H_ 28 #define _MVSDIOREG_H_ 29 30 #define MVSDIO_SIZE 0x10000 31 32 #ifndef MVSDIO_MAX_CLOCK 33 #define MVSDIO_MAX_CLOCK (50 * 1000) /* 50,000 kHz */ 34 #endif /* MVSDIO_MAX_CLOCK */ 35 36 #define MVSDIO_DMABA16LSB 0x0000 /* DMA Buffer Address 16 LSB */ 37 #define MVSDIO_DMABA16MSB 0x0004 /* DMA Buffer Address 16 MSB */ 38 #define MVSDIO_DBS 0x0008 /* Data Block Size */ 39 #define DBS_BLOCKSIZE_MASK 0xfff 40 #define DBS_BLOCKSIZE(s) ((s) & DBS_BLOCKSIZE_MASK) 41 #define DBS_BLOCKSIZE_MAX 0x800 42 #define MVSDIO_DBC 0x000c /* Data Block Count */ 43 #define DBC_BLOCKCOUNT_MASK 0xfff 44 #define DBC_BLOCKCOUNT(c) ((c) & DBC_BLOCKCOUNT_MASK) 45 #define MVSDIO_AC16LSB 0x0010 /* Argument in Command 16 LSB */ 46 #define MVSDIO_AC16MSB 0x0014 /* Argument in Command 16 MSB */ 47 #define MVSDIO_TM 0x0018 /* Transfer Mode */ 48 #define TM_SWWRDATASTART (1 << 0) /* InitWrDataXfer */ 49 #define TM_HWWRDATAEN (1 << 1) /* SWInitWrDataXfer */ 50 #define TM_AUTOCMD12EN (1 << 2) /* SWIssuesCMD12 */ 51 #define TM_INTCHKEN (1 << 3) /* CheckInterrupts */ 52 #define TM_DATAXFERTOWARDHOST (1 << 4) /* XferDataToSDHost */ 53 #define TM_STOPCLKEN (1 << 5) /* StopSDClocks */ 54 #define TM_HOSTXFERMODE (1 << 6) /* SW Write */ 55 #define MVSDIO_C 0x001c /* Command */ 56 #define C_RESPTYPE_NR (0 << 0) /* NoResponse */ 57 #define C_RESPTYPE_136BR (1 << 0) /* 136BitResponse */ 58 #define C_RESPTYPE_48BR (2 << 0) /* 48BitResponse */ 59 #define C_RESPTYPE_48BRCB (3 << 0) /*48BitResponseChkBusy*/ 60 #define C_DATACRC16CHKEN (1 << 2) /* EnableCrc16Chk */ 61 #define C_CMDCRCCHKEN (1 << 3) /* HCCrcChk */ 62 #define C_CMDINDEXCHKEN (1 << 4) /* HCChkIndex */ 63 #define C_DATAPRESENT (1 << 5) /* DataAwaitsTransfer */ 64 #define C_UNEXPECTEDRESPEN (1 << 7) /* UnexpectedRespEn */ 65 #define C_CMDINDEX(c) ((c) << 8) 66 #define MVSDIO_NRH 8 67 #define MVSDIO_RH(n) (0x0020 + ((n) << 2)) /* Response Halfword n */ 68 #define RH_MASK 0xffff 69 #define MVSDIO_16DWACPU 0x0040 /* 16-bit Data Word Accessed by CPU */ 70 #define MVSDIO_CRC7lR 0x0044 /* CRC7 of l Response */ 71 #define CRC7lR_CRC7RESPTOKEN_MASK 0x7f 72 #define MVSDIO_HPS16LSB 0x0048 /* Host Present State 16 LSB */ 73 #define HPS16LSB_CMDINHIBITCMD (1 << 0) /* CmdRegWrite */ 74 #define HPS16LSB_CARDBUSY (1 << 1) /* Card Busy */ 75 #define HPS16LSB_DATLEVEL(x) (((x) >> 3) & 0xf) /* DAT[3:0] Line Signal Level */ 76 #define HPS16LSB_CMDLEVEL (1 << 7) /* CMD line Signal Level */ 77 #define HPS16LSB_TXACTIVE (1 << 8) /* TxEnabled */ 78 #define HPS16LSB_RXACTIVE (1 << 9) /* RxDisabled */ 79 #define HPS16LSB_FIFOFULL (1 << 12) /* FIFO Full */ 80 #define HPS16LSB_FIFOEMPTY (1 << 13) /* FIFO Empty */ 81 #define HPS16LSB_AUTOCMD12ACTIVE (1 << 14) /*auto_cmd12 is active*/ 82 #define MVSDIO_HC 0x0050 /* Host Control */ 83 #define HC_PUSHPULLEN (1 << 0) /* PushPullEn */ 84 #define HC_CARDTYPE_MASK (3 << 1) /* Card type */ 85 #define HC_CARDTYPE_MEMORYONLY (0 << 1) /* Mem only SD card */ 86 #define HC_CARDTYPE_IOONLY (1 << 1) /* IO only SD card */ 87 #define HC_CARDTYPE_IOMEMCOMBO (2 << 1) /* IO and mem combo */ 88 #define HC_CARDTYPE_MMC (3 << 1) /* MMC card */ 89 #define HC_BIGENDIAN (1 << 3) /* BigEndian */ 90 #define HC_LSBFIRST (1 << 4) /* LSB */ 91 #define HC_DATAWIDTH (1 << 9) /* Data Width */ 92 #define HC_HISPEEDEN (1 << 10) /* HighSpeedEnable */ 93 #define HC_TIMEOUTVALUE_MAX (0xf << 11) 94 #define HC_TIMEOUTEN (1 << 15) /* Timeout */ 95 #define MVSDIO_DBGC 0x0054 /* Data Block Gap Control */ 96 #define DBGC_STOPATBLOCKGAPREQ (1 << 0) /* Stop at block gap request */ 97 #define DBGC_CONTREQ (1 << 1) /* Continue request */ 98 #define DBGC_RDWAITCTL (1 << 2) /* EnableRdWait */ 99 #define DBGC_STOPDATXFER (1 << 3) /* StopDataXferEn */ 100 #define DBGC_RESUME (1 << 4) 101 #define DBGC_SUSPEND (1 << 5) 102 #define MVSDIO_CC 0x0058 /* Clock Control */ 103 #define CC_SCLKMASTEREN (1 << 0) /* SdclkEn */ 104 #define MVSDIO_SR 0x005c /* Software Reset */ 105 #define SR_SWRESET (1 << 8) 106 107 #define MVSDIO_NIS 0x0060 /* Normal Interrupt Status */ 108 #define MVSDIO_NISE 0x0068 /* Normal Interrupt Status Enable */ 109 #define MVSDIO_NISIE 0x0070 /* Normal Intr Status Intr Enable */ 110 #define NIS_CMDCOMPLETE (1 << 0) /* Command Complete */ 111 #define NIS_XFERCOMPLETE (1 << 1) /* Transfer Complete */ 112 #define NIS_BLOCKGAPEV (1 << 2) /* Block gap event */ 113 #define NIS_DMAINT (1 << 3) /* DMA interrupt */ 114 #define NIS_TXRDY (1 << 4) 115 #define NIS_RXRDY (1 << 5) 116 #define NIS_CARDINT (1 << 8) /* Card interrupt */ 117 #define NIS_READWAITON (1 << 9) /* Read Wait state is on */ 118 #define NIS_IMBFIFO8WFULL (1 << 10) 119 #define NIS_IMBFIFO8WAVAIL (1 << 11) 120 #define NIS_SUSPENSEON (1 << 12) 121 #define NIS_AUTOCMD12COMPLETE (1 << 13) /* Auto_cmd12 is comp */ 122 #define NIS_UNEXPECTEDRESPDET (1 << 14) 123 #define NIS_ERRINT (1 << 15) /* Error interrupt */ 124 #define MVSDIO_EIS 0x0064 /* Error Interrupt Status */ 125 #define MVSDIO_EISE 0x006c /* Error Interrupt Status Enable */ 126 #define MVSDIO_EISIE 0x0074 /* Error Intr Status Interrupt Enable */ 127 #define EIS_CMDTIMEOUTERR (1 << 0) /*Command timeout err*/ 128 #define EIS_CMDCRCERR (1 << 1) /* Command CRC Error */ 129 #define EIS_CMDENDBITERR (1 << 2) /*Command end bit err*/ 130 #define EIS_CMDINDEXERR (1 << 3) /*Command Index Error*/ 131 #define EIS_DATATIMEOUTERR (1 << 4) /* Data timeout error */ 132 #define EIS_RDDATACRCERR (1 << 5) /* Read data CRC err */ 133 #define EIS_RDDATAENDBITERR (1 << 6) /*Rd data end bit err*/ 134 #define EIS_AUTOCMD12ERR (1 << 8) /* Auto CMD12 error */ 135 #define EIS_CMDSTARTBITERR (1 << 9) /*Cmd start bit error*/ 136 #define EIS_XFERSIZEERR (1 << 10) /*Tx size mismatched err*/ 137 #define EIS_RESPTBITERR (1 << 11) /* Response T bit err */ 138 #define EIS_CRCENDBITERR (1 << 12) /* CRC end bit error */ 139 #define EIS_CRCSTARTBITERR (1 << 13) /* CRC start bit err */ 140 #define EIS_CRCSTATERR (1 << 14) /* CRC status error */ 141 142 #define MVSDIO_ACMD12IS 0x0078 /* Auto CMD12 Interrupt Status */ 143 #define ACMD12IS_AUTOCMD12NOTEXE (1 << 0) 144 #define ACMD12IS_AUTOCMD12TIMEOUTER (1 << 1) 145 #define ACMD12IS_AUTOCMD12CRCER (1 << 2) 146 #define ACMD12IS_AUTOCMD12ENDBITER (1 << 3) 147 #define ACMD12IS_AUTOCMD12INDEXER (1 << 4) 148 #define ACMD12IS_AUTOCMD12RESPTBITER (1 << 5) 149 #define ACMD12IS_AUTOCMD12RESPSTARTBITER (1 << 6) 150 #define MVSDIO_CNBRDB 0x007c/*Current Num of Bytes Remaining in Data*/ 151 #define MVSDIO_CNDBLBT 0x0080/*Current Num of Data Blk Left ToBe Txed*/ 152 #define MVSDIO_AACC16LSBT 0x0084 /*Arg in Auto Cmd12 Command 16 LSB Txed*/ 153 #define MVSDIO_AACC16MSBT 0x0088 /*Arg in Auto Cmd12 Command 16 MSB Txed*/ 154 #define MVSDIO_IACCT 0x008c /* Index of Auto Cmd12 Commands Tx-ed */ 155 #define IACCT_AUTOCMD12BUSYCHKEN (1 << 0) 156 #define IACCT_AUTOCMD12INDEXCHKEN (1 << 1) 157 #define IACCT_AUTOCMD12INDEX (MMC_STOP_TRANSMISSION << 8) 158 #define MVSDIO_ACRH(n) (0x0090 + ((n) << 2)) /* Auto Cmd12 Response Halfword n */ 159 160 161 #define MVSDIO_MCL 0x0100 /* Mbus Control Low */ 162 #define MVSDIO_MCH 0x0104 /* Mbus Control High */ 163 #define MCL_SDARBENTRY(n, x) (((x) & 0xf) << ((n) << 2)) 164 165 #define MVSDIO_NWINDOW 4 166 #define MVSDIO_WC(n) (0x0108 + ((n) << 3)) /* Window n Control */ 167 #define WC_WINEN (1 << 0) /* Window n Enable */ 168 #define WC_TARGET(t) (((t) & 0xf) << 4) 169 #define WC_ATTR(a) (((a) & 0xff) << 8) 170 #define WC_SIZE(s) (((s) - 1) & 0xffff0000) 171 #define MVSDIO_WB(n) (0x010c + ((n) << 3)) /* Window n Base */ 172 #define WB_BASE(b) ((b) & 0xffff0000) 173 #define MVSDIO_CDV 0x0128 /* Clock Divider Value */ 174 #define CDV_CLKDVDRMVALUE_MASK 0x7ff 175 #define MVSDIO_ADE 0x012c /* Address Decoder Error */ 176 #define ADE_ADD_DEC_MISS_ERR (1 << 0) 177 #define ADE_ADD_DEC_MULTI_ERR (1 << 1) 178 #define MVSDIO_ADEM 0x0130 /* Address Decoder Error Mask */ 179 #define ADEM_VARIOUS(x) ((x) << 0) /* Do not mask */ 180 181 #endif /* _MVSDIOREG_H_ */ 182