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Searched refs:HI (Results 1 – 25 of 369) sorted by relevance

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/netbsd/src/external/gpl3/gcc/dist/gcc/config/h8300/
Ddivmod.md46 (udiv:HI
47 (match_operand:HI 1 "register_operand" "0")
48 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
51 (umod:HI
53 (zero_extend:HI (match_dup 2)))))]
58 (udiv:HI (match_dup 1)
59 (zero_extend:HI (match_dup 2)))))
61 (umod:HI (match_dup 1)
62 (zero_extend:HI (match_dup 2)))))
69 (udiv:HI
[all …]
Dmova.md57 [(set (match_operand:HI 0 "register_operand" "=r,r")
58 (plus:HI (zero_extend:HI (match_operand:QI 1 "h8300_dst_operand" "0,rQ"))
59 (match_operand:HI 2 "immediate_operand" "i,i")))]
65 [(set (match_operand:HI 0 "register_operand" "=r,r")
66 (mult:HI (zero_extend:HI (match_operand:QI 1 "h8300_dst_operand" "0,rQ"))
73 [(set (match_operand:HI 0 "register_operand" "=r,r")
74 (plus:HI (mult:HI (zero_extend:HI (match_operand:QI 1 "h8300_dst_operand" "0,rQ"))
76 (match_operand:HI 2 "immediate_operand" "i,i")))]
82 [(set (match_operand:HI 0 "register_operand" "=r")
83 (and:HI (mult:HI (subreg:HI (match_operand:QI 1 "memory_operand" "m") 0)
[all …]
Dmultiply.md8 [(set (match_operand:HI 0 "register_operand" "")
9 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
19 [(set (match_operand:HI 0 "register_operand" "=r")
20 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
26 (mult:HI (sign_extend:HI (match_dup 1)) (match_dup 2)))
30 [(set (match_operand:HI 0 "register_operand" "=r")
31 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
39 [(set (match_operand:HI 0 "register_operand" "=r")
40 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
41 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
[all …]
Dpeepholes.md8 [(parallel [(set (match_operand:HI 0 "register_operand" "")
9 (lshiftrt:HI (match_dup 0)
10 (match_operand:HI 1 "const_int_operand" "")))
11 (clobber (match_operand:HI 2 "" ""))])
13 (and:HI (match_dup 0)
14 (match_operand:HI 3 "const_int_operand" "")))]
17 (and:HI (match_dup 0)
20 (lshiftrt:HI (match_dup 0) (match_dup 1)))
27 [(parallel [(set (match_operand:HI 0 "register_operand" "")
28 (ashift:HI (match_dup 0)
[all …]
Dbitfield.md19 [(set (match_operand:HI 0 "register_operand" "=&r")
20 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
21 (match_operand:HI 3 "const_int_operand" "n"))
23 (match_operand:HI 2 "const_int_operand" "n")))]
29 (zero_extract:HI (xor:HI (match_dup 1) (match_dup 3))
35 [(set (match_operand:HI 0 "register_operand" "=&r")
36 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
37 (match_operand:HI 3 "const_int_operand" "n"))
39 (match_operand:HI 2 "const_int_operand" "n")))
109 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
[all …]
Dcombiner.md253 (ashift:HI (match_dup 5)
341 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
354 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))
410 ;; [ix]or:HI
413 [(set (match_operand:HI 0 "register_operand" "=r")
414 (match_operator:HI 1 "iorxor_operator"
415 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
416 (match_operand:HI 3 "register_operand" "0")]))]
421 (match_op_dup 1 [(zero_extend:HI (match_dup 2))
427 [(set (match_operand:HI 0 "register_operand" "=r")
[all …]
Dextensions.md15 [(set (match_operand:HI 0 "register_operand" "=r,r")
16 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
20 [(parallel [(set (match_dup 0) (zero_extend:HI (match_dup 1)))
24 [(set (match_operand:HI 0 "register_operand" "=r,r")
25 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))
39 [(set (match_operand:HI 0 "register_operand" "")
40 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))
44 (parallel [(set (match_dup 0) (zero_extend:HI (match_dup 2)))
66 (parallel [(set (match_dup 3) (zero_extend:HI (match_dup 2)))
108 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
[all …]
Dgenmova.sh45 for s in QI HI; do
50 HI) src=%T1.w;;
59 for d in QI HI SI; do
66 SI:QI | SI:HI | HI:QI)
92 HI:1) mask=131070;;
93 HI:2) mask=262140;;
108 QI:QI | HI:HI)
125 SI:QI | SI:HI | HI:QI)
Daddsub.md32 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
33 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
34 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
38 [(parallel [(set (match_dup 0) (plus:HI (match_dup 1) (match_dup 2)))
42 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
43 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
44 (match_operand:HI 2 "h8300_src_operand" "M,O,J,n,r")))
79 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
80 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
81 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/stormy16/
Dstormy16.md117 [(set (mem:QI (post_inc:HI (reg:HI 15)))
126 (mem:QI (pre_dec:HI (reg:HI 15))))]
171 [(set (mem:HI (post_inc:HI (reg:HI 15)))
172 (match_operand:HI 0 "register_operand" "r"))]
179 [(set (match_operand:HI 0 "register_operand" "=r")
180 (mem:HI (pre_dec:HI (reg:HI 15))))]
187 [(set (match_operand:HI 0 "nonimmediate_nonstack_operand" "")
188 (match_operand:HI 1 "general_operand" ""))]
195 [(set (match_operand:HI 0 "nonimmediate_nonstack_operand" "=r,m,e,e,T,r,S,W,e")
196 (match_operand:HI 1 "general_operand" "r,e,m,L,L,i,i,ie,W"))]
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/m32c/
Dmuldiv.md25 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
26 (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
35 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
36 (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
37 … (sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
45 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
46 (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
54 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
55 (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
63 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
[all …]
Dblkmov.md64 [(set (mem:QI (match_operand:HI 3 "ap_operand" "0"))
65 (mem:QI (match_operand:HI 4 "ap_operand" "1")))
66 (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
68 (set (match_operand:HI 0 "ap_operand" "=Ra1")
69 (plus:HI (match_dup 3)
70 (zero_extend:HI (match_operand:HI 5 "m32c_r3_operand" "2"))))
71 (set (match_operand:HI 1 "ap_operand" "=Ra0")
72 (plus:HI (match_dup 4)
73 (zero_extend:HI (match_dup 5))))
74 (use (reg:HI R1_REGNO))]
[all …]
Dshift.md35 (clobber (match_scratch:HI 3 "=X,R1w"))]
47 (clobber (match_scratch:HI 3 "=X,R1w"))]
59 (clobber (match_scratch:HI 3 "=X,R1w"))]
72 (clobber (match_scratch:HI 3 ""))])]
82 (clobber (match_scratch:HI 3 ""))])]
92 (clobber (match_scratch:HI 3 ""))])]
101 [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
102 (ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
104 (clobber (match_scratch:HI 3 "=X,R1w"))]
113 [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
[all …]
Dmov.md32 (mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "Ra0"))
41 [(set (mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "Ra0"))
80 [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
82 (match_operand:HI 1 "m32c_any_operand"
101 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhiSd*Rmm")
102 (match_operand:HI 1 "m32c_any_operand" "iRhiSd*Rmm"))]
164 [(set (match_operand:HI 0 "memory_operand" "")
165 (match_operand:HI 1 "const_int_operand" ""))
166 (set (match_operand:HI 2 "memory_operand" "")
167 (match_operand:HI 3 "const_int_operand" ""))]
[all …]
Dbitops.md43 (ior:QI (subreg:QI (ashift:HI (const_int 1)
44 … (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
52 [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
54 … (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
68 [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
70 … (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
98 [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm")
99 (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
100 (match_operand:HI 2 "mrai_operand" "ImB,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
161 [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm")
[all …]
Dprologue.md34 [(set (mem:HI (plus:HI (reg:HI SP_REGNO) (const_int -2)))
35 (reg:HI FB_REGNO))
36 (set (reg:HI FB_REGNO)
37 (plus:HI (reg:HI SP_REGNO) (const_int -2)))
38 (set (reg:HI SP_REGNO)
39 (minus:HI (reg:HI SP_REGNO)
107 [(set (reg:HI SP_REGNO)
108 (plus:HI (reg:HI FB_REGNO)
110 (set (reg:HI FB_REGNO)
111 (mem:HI (reg:HI FB_REGNO)))
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/avr/
Davr.md44 ;; Example: With %0 = (reg:HI 18) and %1 = (const_int 13)
48 ;; Example: With %0 = (reg:HI 18) and %1 = (const_int 13)
250 (define_mode_iterator QIHI [QI HI])
251 (define_mode_iterator QIHI2 [QI HI])
252 (define_mode_iterator QISI [QI HI PSI SI])
253 (define_mode_iterator QIDI [QI HI PSI SI DI])
254 (define_mode_iterator QIPSI [QI HI PSI])
255 (define_mode_iterator HISI [HI PSI SI])
259 (define_mode_iterator ALL2 [HI HQ UHQ HA UHA])
261 (define_mode_iterator ALL234 [HI SI PSI
[all …]
/netbsd/src/external/gpl3/gdb/dist/sim/common/
Dcgen-ops.h92 #define ADDHI(x, y) ((HI) ((UHI) (x) + (UHI) (y)))
93 #define SUBHI(x, y) ((HI) ((UHI) (x) - (UHI) (y)))
94 #define MULHI(x, y) ((HI) ((UHI) (x) * (UHI) (y)))
95 #define DIVHI(x, y) ((HI) (x) / (HI) (y))
97 #define MODHI(x, y) ((HI) (x) % (HI) (y))
99 #define SRAHI(x, y) ((HI) (x) >> (y))
102 extern HI RORHI (HI, int);
103 extern HI ROLHI (HI, int);
107 #define NEGHI(x) ((HI) (- (UHI) (x)))
108 #define NOTHI(x) (! (HI) (x))
[all …]
/netbsd/src/sys/external/bsd/sljit/dist/sljit_src/
DsljitNativePPC_common.c135 #define HI(opcode) ((opcode) << 26) macro
138 #define ADD (HI(31) | LO(266))
139 #define ADDC (HI(31) | LO(10))
140 #define ADDE (HI(31) | LO(138))
141 #define ADDI (HI(14))
142 #define ADDIC (HI(13))
143 #define ADDIS (HI(15))
144 #define ADDME (HI(31) | LO(234))
145 #define AND (HI(31) | LO(28))
146 #define ANDI (HI(28))
[all …]
DsljitNativeMIPS_common.c90 #define HI(opcode) ((opcode) << 26) macro
95 #define ABS_S (HI(17) | FMT_S | LO(5))
96 #define ADD_S (HI(17) | FMT_S | LO(0))
97 #define ADDIU (HI(9))
98 #define ADDU (HI(0) | LO(33))
99 #define AND (HI(0) | LO(36))
100 #define ANDI (HI(12))
101 #define B (HI(4))
102 #define BAL (HI(1) | (17 << 16))
103 #define BC1F (HI(17) | (8 << 21))
[all …]
/netbsd/src/external/gpl3/binutils/dist/include/cgen/
Dbasic-ops.h89 #define DIVHI(x, y) ((HI) (x) / (HI) (y))
91 #define MODHI(x, y) ((HI) (x) % (HI) (y))
93 #define SRAHI(x, y) ((HI) (x) >> (y))
96 extern HI RORHI (HI, int);
97 extern HI ROLHI (HI, int);
102 #define NOTHI(x) (! (HI) (x))
105 #define EQHI(x, y) ((HI) (x) == (HI) (y))
106 #define NEHI(x, y) ((HI) (x) != (HI) (y))
107 #define LTHI(x, y) ((HI) (x) < (HI) (y))
108 #define LEHI(x, y) ((HI) (x) <= (HI) (y))
[all …]
/netbsd/src/external/gpl3/gdb/dist/include/cgen/
Dbasic-ops.h89 #define DIVHI(x, y) ((HI) (x) / (HI) (y))
91 #define MODHI(x, y) ((HI) (x) % (HI) (y))
93 #define SRAHI(x, y) ((HI) (x) >> (y))
96 extern HI RORHI (HI, int);
97 extern HI ROLHI (HI, int);
102 #define NOTHI(x) (! (HI) (x))
105 #define EQHI(x, y) ((HI) (x) == (HI) (y))
106 #define NEHI(x, y) ((HI) (x) != (HI) (y))
107 #define LTHI(x, y) ((HI) (x) < (HI) (y))
108 #define LEHI(x, y) ((HI) (x) <= (HI) (y))
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/bfin/
Dbfin.md411 (define_mode_iterator CCMOV [QI HI SI])
669 [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
670 (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
812 [(set (match_operand:HI 0 "nonimmediate_operand" "")
813 (match_operand:HI 1 "general_operand" ""))]
874 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x"))
875 (match_operand:HI 1 "immediate_operand" "Ksh"))]
885 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
900 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
921 [(set (match_operand:HI 0 "register_operand" "=d, d")
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/pdp11/
Dpdp11.md67 ;; HI is 16 bit
72 (define_mode_iterator PDPint [QI HI])
73 (define_mode_attr isfx [(QI "b") (HI "")])
74 (define_mode_attr mname [(QI "QImode") (HI "HImode") (SI "SImode") (DI "DImode")])
75 (define_mode_attr e_mname [(QI "E_QImode") (HI "E_HImode") (SI "E_SImode") (DI "E_DImode")])
76 (define_mode_attr hmode [(QI "hi") (HI "hi") (SI "si") (DI "di")])
79 (define_mode_iterator HSint [HI SI])
80 (define_mode_iterator QHSint [QI HI SI])
81 (define_mode_iterator QHSDint [QI HI SI DI])
329 (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m")
[all …]
/netbsd/src/external/gpl3/gdb/dist/sim/mips/
Dsmartmips.igen52 HI ^= EXTEND32 (VH4_8 (res));
53 TRACE_ALU_RESULT2 (HI, LO);
62 TRACE_ALU_INPUT3 (ACX,HI,LO);
64 LO = HI;
65 HI = ACX;
67 TRACE_ALU_RESULT4 (ACX,HI,LO,GPR[RD]);
75 TRACE_ALU_INPUT3 (HI,LO,GPR[RS]);
76 ACX = HI;
77 HI = LO;
79 TRACE_ALU_RESULT4 (ACX,HI,LO,GPR[RS]);
[all …]

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