1/*        $NetBSD: locore_machdep.S,v 1.2 2020/01/12 13:15:10 tsutsui Exp $     */
2
3/*-
4 * Copyright (c) 2010 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code was written by Alessandro Forin and Neil Pittman
8 * at Microsoft Research and contributed to The NetBSD Foundation
9 * by Microsoft Corporation.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *    notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *    notice, this list of conditions and the following disclaimer in the
18 *    documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
34 * Access to the eMIPS special registers.
35 */
36
37#include <mips/asm.h>
38#include <mips/cpuregs.h>
39
40          .set      noreorder
41          .set      mips32
42
43#define MIPS_COP_0_EXT_CTL  _(22)
44#define MIPS_COP_0_EXT_MISS _(23)
45#define MIPS_COP_0_EXT_HIT  _(24)
46
47/*
48 * Extension control register bits, definitions and semantics
49 */
50/*
51 * The Opcode field holds the opcode assigned to the given Extension slot (Z).
52 * When this field is written to, the CAM used for decoding the Extension
53 * Instructions is updated (in CAM Decoding mode).  The value can be one
54 * of the eight Extension Opcodes, or any other opcode iff the Extension
55 * has priority and is meant to mask an existing instruction.
56 */
57#define EXTCTL_OP       0xfc000000
58/*
59 * The Kernel/User flag denotes that Extension Z is a Kernel[0] or User[1]
60 * mode Extension.
61 */
62#define EXTCTL_KU       0x02000000
63/*
64 * The Scope flag denotes that Extension Z is a Local[0] (per process) or
65 * Global[1] (shared) Extension.
66 */
67#define EXTCTL_SC       0x01000000
68/*
69 * The Peripheral flag denotes that Extension Z is a Peripheral Extension.
70 */
71#define EXTCTL_PER      0x00080000
72/*
73 * The Interrupt flag denotes that Extension Z has an interrupt.
74 */
75#define EXTCTL_INT      0x00040000
76/*
77 * The Virtual/Physical flag denotes that Extension Z uses Virtual[0] or
78 * Physical[0] addresses when accessing the memory bus.
79 */
80#define EXTCTL_VP       0x00020000
81/*
82 * The State field denotes the state of Extension Z.  (Loaded, Config,
83 * Running, Suspend, etc)
84 */
85#define EXTCTL_ST       0x0000f000
86/*
87 * The Priority field denotes the execution priority for Extension Z
88 * during arbitration.
89 */
90#define EXTCTL_PR       0x00000f00
91/*
92 * The Privileged flag denotes that Extension Z has access to security
93 * sensitive system resources.
94 */
95#define EXTCTL_PRV      0x00000080
96/*
97 * The Trap flag denotes whether an RI exception will be generated for
98 * an Extension Z's instruction if Extension Z is disabled.
99 */
100#define EXTCTL_TR       0x00000010
101/*
102 * The Trapped flag denotes that a trap occurred during Extension Z's
103 * last execution and it was unable to complete.
104 */
105#define EXTCTL_TD       0x00000008
106/*
107 * The Clock Enable flag denotes that the clock for Extension Z is active.
108 */
109#define EXTCTL_CE       0x00000004
110/*
111 * The Enable flag denotes that Extension Z is enabled for execution.
112 */
113#define EXTCTL_EN       0x00000002
114/*
115 * The Loaded flag denotes that Extension Z has been loaded
116 */
117#define EXTCTL_LD       0x00000001
118
119/*
120 * unsigned int acc_get_misses(int op_number);
121 *
122 * Get the number of misses for the given opcode on the current processor
123 * nb: clears the counter too
124 */
125LEAF(acc_get_misses)
126          la        v0, 1f
127          andi      a0, a0, 7
128          sll       a0, a0, 3
129          addu      a0, v0, a0
130          jr      a0
131           nop
1321:
133          j         ra
134           mfc0     v0, MIPS_COP_0_EXT_MISS, 0
135          j         ra
136           mfc0     v0, MIPS_COP_0_EXT_MISS, 1
137          j         ra
138           mfc0     v0, MIPS_COP_0_EXT_MISS, 2
139          j         ra
140           mfc0     v0, MIPS_COP_0_EXT_MISS, 3
141          j         ra
142           mfc0     v0, MIPS_COP_0_EXT_MISS, 4
143          j         ra
144           mfc0     v0, MIPS_COP_0_EXT_MISS, 5
145          j         ra
146           mfc0     v0, MIPS_COP_0_EXT_MISS, 6
147          j         ra
148           mfc0     v0, MIPS_COP_0_EXT_MISS, 7
149END(acc_get_misses)
150
151/*
152 * unsigned int acc_get_hits(int slot_number);
153 *
154 * Get the number of hits for the given accelerator slot on the current
155 * processor
156 * nb: clears the counter too
157 */
158LEAF(acc_get_hits)
159          la        v0, 1f
160          andi      a0, a0, 7
161          sll       a0, a0, 3
162          addu      a0, v0, a0
163          jr        a0
164           nop
1651:
166          j         ra
167           mfc0     v0, MIPS_COP_0_EXT_HIT, 0
168          j         ra
169           mfc0     v0, MIPS_COP_0_EXT_HIT, 1
170          j         ra
171           mfc0     v0, MIPS_COP_0_EXT_HIT, 2
172          j         ra
173           mfc0     v0, MIPS_COP_0_EXT_HIT, 3
174          j         ra
175           mfc0     v0, MIPS_COP_0_EXT_HIT, 4
176          j         ra
177           mfc0     v0, MIPS_COP_0_EXT_HIT, 5
178          j         ra
179           mfc0     v0, MIPS_COP_0_EXT_HIT, 6
180          j         ra
181           mfc0     v0, MIPS_COP_0_EXT_HIT, 7
182END(acc_get_hits)
183
184/*
185 * unsigned int acc_activate(int slot_number, uint32_t value);
186 *
187 * Make the given accelerator slot in/active
188 * Returns the previous value in the control register
189 */
190LEAF(acc_activate)
191          la        v0, 1f
192          andi      a0, a0, 7
193          sll       a0, a0, 4
194          addu      a0, v0, a0
195          jr        a0
196           nop
1971:
198          mfc0      v0, MIPS_COP_0_EXT_CTL, 0
199          mtc0      a1, MIPS_COP_0_EXT_CTL, 0
200          j         ra
201           nop
202
203          mfc0      v0, MIPS_COP_0_EXT_CTL, 1
204          mtc0      a1, MIPS_COP_0_EXT_CTL, 1
205          j         ra
206           nop
207
208          mfc0      v0, MIPS_COP_0_EXT_CTL, 2
209          mtc0      a1, MIPS_COP_0_EXT_CTL, 2
210          j         ra
211           nop
212
213          mfc0      v0, MIPS_COP_0_EXT_CTL, 3
214          mtc0      a1, MIPS_COP_0_EXT_CTL, 3
215          j         ra
216           nop
217
218          mfc0      v0, MIPS_COP_0_EXT_CTL, 4
219          mtc0      a1, MIPS_COP_0_EXT_CTL, 4
220          j         ra
221           nop
222
223          mfc0      v0, MIPS_COP_0_EXT_CTL, 5
224          mtc0      a1, MIPS_COP_0_EXT_CTL, 5
225          j         ra
226           nop
227
228          mfc0      v0, MIPS_COP_0_EXT_CTL, 6
229          mtc0      a1, MIPS_COP_0_EXT_CTL, 6
230          j         ra
231           nop
232
233          mfc0      v0, MIPS_COP_0_EXT_CTL, 7
234          mtc0      a1, MIPS_COP_0_EXT_CTL, 7
235          j         ra
236           nop
237END(acc_activate)
238