1 /* $NetBSD: imxecspireg.h,v 1.4 2023/08/01 21:26:27 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2012 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_IMX_IMXECSPIREG_H_ 30 #define _ARM_IMX_IMXECSPIREG_H_ 31 32 #define ECSPI_RXDATA 0x00 33 #define ECSPI_TXDATA 0x04 34 #define ECSPI_CONREG 0x08 35 #define ECSPI_CON_BITCOUNT __BITS(31,20) 36 #define ECSPI_CON_CS __BITS(19,18) 37 #define ECSPI_CON_DRCTL __BITS(17,16) 38 #define ECSPI_CON_PREDIV __BITS(15,12) /* PRE DIVIDER */ 39 #define ECSPI_CON_DIV __BITS(11, 8) /* POST DIVIDER */ 40 #define ECSPI_CON_MODE __BITS( 7, 4) /* MODE */ 41 #define ECSPI_CON_SMC __BIT(3) /* SMC */ 42 #define ECSPI_CON_XCH __BIT(2) /* XCH */ 43 #define ECSPI_CON_HW __BIT(1) /* HW */ 44 #define ECSPI_CON_ENABLE __BIT(0) /* EN */ 45 #define ECSPI_CONFIGREG 0x0c 46 #define ECSPI_CONFIG_HT_LEN __BITS(28,24) /* HT LENGTH */ 47 #define ECSPI_CONFIG_SCLK_CTL __BITS(23,20) /* SCLK CTL */ 48 #define ECSPI_CONFIG_DATA_CTL __BITS(19,16) /* DATA CTL */ 49 #define ECSPI_CONFIG_SSB_POL __BITS(15,12) /* SSB POL */ 50 #define ECSPI_CONFIG_SSB_CTL __BITS(11, 8) /* SSB CTL */ 51 #define ECSPI_CONFIG_SCLK_POL __BITS( 7, 4) /* SCLK POL */ 52 #define ECSPI_CONFIG_SCLK_PHA __BITS( 3, 0) /* SCLK PHA */ 53 #define ECSPI_INTREG 0x10 54 #define ECSPI_INTR_ALL_EN __BITS( 7, 0) /* All Interrupts Enabled */ 55 #define ECSPI_INTR_TC_EN __BIT(7) /* TX Complete */ 56 #define ECSPI_INTR_RO_EN __BIT(6) /* RXFIFO Overflow */ 57 #define ECSPI_INTR_RF_EN __BIT(5) /* RXFIFO Full */ 58 #define ECSPI_INTR_RD_EN __BIT(4) /* RXFIFO Data Request */ 59 #define ECSPI_INTR_RR_EN __BIT(3) /* RXFIFO Ready */ 60 #define ECSPI_INTR_TF_EN __BIT(2) /* TXFIFO Full */ 61 #define ECSPI_INTR_TD_EN __BIT(1) /* TXFIFO Data Request */ 62 #define ECSPI_INTR_TE_EN __BIT(0) /* TXFIFO Empty */ 63 #define ECSPI_DMAREG 0x14 64 #define ECSPI_STATREG 0x18 65 #define ECSPI_STAT_CLR_TC __BIT(7) /* Clear Transfer Completed */ 66 #define ECSPI_STAT_CLR_RO __BIT(6) /* Clear RXFIFO Overflow */ 67 #define ECSPI_STAT_CLR ECSPI_STAT_CLR_TC 68 #define ECSPI_STAT_RF __BIT(5) 69 #define ECSPI_STAT_RDR __BIT(4) 70 #define ECSPI_STAT_RR __BIT(3) 71 #define ECSPI_STAT_TF __BIT(2) 72 #define ECSPI_STAT_TDR __BIT(1) 73 #define ECSPI_STAT_TE __BIT(0) 74 #define ECSPI_PERIODREG 0x1c 75 #define ECSPI_TESTREG 0x20 76 #define ECSPI_MSGDATA 0x40 77 78 #define ECSPI_SIZE 0x50 79 80 #endif /* _ARM_IMX_IMXECSPIREG_H_ */ 81