1 /*
2  * $NetBSD: drcustom.h,v 1.8 2003/04/09 01:54:43 thorpej Exp $
3  *
4  * Motherboard addresses for the DraCo.
5  *
6  */
7 
8 #ifndef _DRACO_HARDWARE
9 #define _DRACO_HARDWARE
10 
11 /*
12  * CIA-B is available only in very early models.
13  * CIA-A is available only up to revision 3.
14  */
15 
16 #define DRCIABASE 0x02800000
17 #define DRCIATOP  0x02802000
18 #define NDRCIAPG ((DRCIATOP - DRCIABASE) / PAGE_SIZE)       /* which is 1 */
19 
20 #define NDRCCPG (8+1+1) /* (3 int+msc+ctrl+superio+cia+1stkick)+scsi+altais */
21 
22 #define DRCCBASE    0x01000000
23 #define DRCCSTRIDE  0x00400000          /* for up to and including 1st kick pg */
24 
25 #define DRZ2BASE    0x03000000          /*
26                                                    * not really used, appears as Z3 to
27                                                    * our kernel.
28                                                    */
29 #define DRSCSIBASE  0x04000000
30 
31 #define DR_INTENA (DRCCBASE+0x1)
32 #define DR_INTPEN (DRCCBASE+0x00400001)
33 #define DR_INTFRC (DRCCBASE+0x00800001)
34 
35 #define DRIRQ_GLOBAL          1         /* not force */
36 #define DRIRQ_SOFT DRIRQ_GLOBAL         /* only force */
37 #define DRIRQ_SCSI  2
38 #define DRIRQ_INT2  4
39 #define DRIRQ_INT6  8
40 
41 
42 /* mapped state: */
43 #define   DRMISCPG 3
44 #define   DRIOCTLPG 4
45 #define   DRSUPIOPG 5
46 #define DRCIAPG 6
47 #define DRKICKPG 7  /*
48                                * kick page, used only as a stopgap delay address
49                                * for early DraCos
50                                */
51 #define DRSCSIPG 8
52 
53 #ifdef _KERNEL
54 #ifndef _LOCORE
55 
56 extern vaddr_t DRCCADDR;
57 
58 extern volatile u_int8_t *draco_intena, *draco_intpen, *draco_intfrc;
59 extern volatile u_int8_t *draco_misc;
60 extern volatile struct drioct *draco_ioct;
61 
62 struct drioct {
63           u_int8_t dum0;
64           volatile u_int8_t io_control; /*  1 */
65 #define DRCNTRL_FDCINTENA 1
66 #define DRCNTRL_KBDDATOUT 2
67 #define DRCNTRL_KBDCLKOUT 4
68 #define DRCNTRL_WDOGDIS 8
69 #define DRCNTRL_WDOGDAT 16
70 #define DRCNTRL_KBDINTENA 32
71 #define DRCNTRL_KBDKBDACK 64
72 #define DRCNTRL_SCSITERM 128
73 
74           u_int8_t dum1;
75           volatile u_int8_t io_status;  /*  3 */
76 #define DRSTAT_CLKDAT 1
77 #define DRSTAT_KBDDATIN 2
78 #define DRSTAT_KBDCLKIN 4
79 #define DRSTAT_KBDRECV 8
80 #define DRSTAT_CLKBUSY 16
81 #define DRSTAT_BUSTIMO 32
82 #define DRSTAT_SCSILED 64
83 
84           u_int8_t dum2;
85           volatile u_int8_t io_kbddata; /*  5 */
86 
87           u_int8_t dum3;
88           volatile u_int8_t io_status2; /*  7 */
89 #define DRSTAT2_KBDBUSY 1
90 #define DRSTAT2_PARIRQPEN 4
91 #define DRSTAT2_PARIRQENA 8
92 #define DRSTAT2_TMRINTENA 16
93 #define DRSTAT2_TMRIRQPEN 32
94 
95           u_int8_t dum4;
96           volatile u_int8_t io_chiprev; /*  9 */
97 #define io_timerrst io_chiprev                    /* on writes */
98 
99           u_int8_t dum5;
100           volatile u_int8_t io_timerhi; /*  b */
101           u_int8_t dum6;
102           volatile u_int8_t io_timerlo; /*  d */
103 
104           u_int8_t dum7[3];   /* nothing @ f, at least yet */
105 
106           volatile u_int8_t io_clockw0; /* 11 */
107           u_int8_t dum8;
108           volatile u_int8_t io_clockw1; /* 13 */
109           u_int8_t dum9;
110           volatile u_int8_t io_clockrst;          /* 15 */
111 
112           u_int8_t dum10;
113           volatile u_int8_t io_kbdrst;  /* 17 */
114 
115           u_int8_t dum11;
116           volatile u_int8_t io_bustimeoutrst;     /* 19 */
117 
118           u_int8_t dum12;
119           volatile u_int8_t io_scsiledrst;        /* 1b */
120 
121           u_int8_t dum13;
122           volatile u_int8_t io_fdcread;           /* 1d */
123 
124           u_int8_t dum14;
125           volatile u_int8_t io_parrst;            /* 1e */
126 
127 };
128 #endif
129 #endif
130 
131 #endif /* _DRACO_HARDWARE */
132