Searched refs:DP_TRAINING_LANE0_SET (Results 1 – 2 of 2) sorted by relevance
465 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training, in anxdp_link_start()510 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training, in anxdp_process_clock_recovery()555 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training, in anxdp_process_eq()
448 #define DP_TRAINING_LANE0_SET 0x103 macro