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Searched refs:CSR_READ_1 (Results 1 – 25 of 29) sorted by relevance

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/netbsd/src/sys/arch/evbarm/stand/boot2440/
Ddm9000.c134 CSR_READ_1(struct local *l, int reg) in CSR_READ_1() function
170 val = CSR_READ_1(l, PID0); in dm9k_match()
171 val |= CSR_READ_1(l, PID1) << 8; in dm9k_match()
172 val |= CSR_READ_1(l, VID0) << 16; in dm9k_match()
173 val |= CSR_READ_1(l, VID1) << 24; in dm9k_match()
195 val = CSR_READ_1(l, CHIPR); in dm9k_init()
197 val = CSR_READ_1(l, ISR); in dm9k_init()
214 } while (NCR_RST & CSR_READ_1(l, NCR)); in dm9k_init()
223 } while (NCR_RST & CSR_READ_1(l, NCR)); in dm9k_init()
226 (void) CSR_READ_1(l, NSR); in dm9k_init()
[all …]
/netbsd/src/sys/arch/sandpoint/stand/altboot/
Dnvt.c48 #define CSR_READ_1(l, r) in8((l)->csr+(r)) macro
185 val = CSR_READ_1(l, VR_CTL1); in nvt_init()
188 l->phy = CSR_READ_1(l, VR_MIICFG) & 0x1f; in nvt_init()
191 en[0] = CSR_READ_1(l, VR_PAR0); in nvt_init()
192 en[1] = CSR_READ_1(l, VR_PAR1); in nvt_init()
193 en[2] = CSR_READ_1(l, VR_PAR2); in nvt_init()
194 en[3] = CSR_READ_1(l, VR_PAR3); in nvt_init()
195 en[4] = CSR_READ_1(l, VR_PAR4); in nvt_init()
196 en[5] = CSR_READ_1(l, VR_PAR5); in nvt_init()
322 v = CSR_READ_1(l, VR_MIISR); in mii_autopoll()
[all …]
Dvge.c48 #define CSR_READ_1(l, r) in8((l)->csr+(r)) macro
232 val = CSR_READ_1(l, VR_CTL1); in vge_init()
235 l->phy = CSR_READ_1(l, VR_MIICFG) & 0x1f; in vge_init()
238 en[0] = CSR_READ_1(l, VR_PAR0); in vge_init()
239 en[1] = CSR_READ_1(l, VR_PAR1); in vge_init()
240 en[2] = CSR_READ_1(l, VR_PAR2); in vge_init()
241 en[3] = CSR_READ_1(l, VR_PAR3); in vge_init()
242 en[4] = CSR_READ_1(l, VR_PAR4); in vge_init()
243 en[5] = CSR_READ_1(l, VR_PAR5); in vge_init()
282 while (--loop > 0 && (i = CSR_READ_1(l, VR_CAMCTL)) & CAMCTL_WR) in vge_init()
[all …]
Ddsk.c59 #define CSR_READ_1(r) in8(r) macro
151 (void)CSR_READ_1(chan->alt); in spinwait_unbusy()
152 (void)CSR_READ_1(chan->alt); in spinwait_unbusy()
153 (void)CSR_READ_1(chan->alt); in spinwait_unbusy()
154 (void)CSR_READ_1(chan->alt); in spinwait_unbusy()
156 sts = CSR_READ_1(chan->cmd + _STS); in spinwait_unbusy()
161 sts = CSR_READ_1(chan->cmd + _STS); in spinwait_unbusy()
201 (void)CSR_READ_1(chan->alt); in wakeup_drive()
205 (void)CSR_READ_1(chan->alt); in wakeup_drive()
215 (void)CSR_READ_1(chan->alt); in atachkpwr()
[all …]
Drge.c48 #define CSR_READ_1(l, r) in8((l)->csr+(r)) macro
161 val = CSR_READ_1(l, RGE_CR); in rge_init()
179 en[0] = CSR_READ_1(l, RGE_IDR0); in rge_init()
180 en[1] = CSR_READ_1(l, RGE_IDR1); in rge_init()
181 en[2] = CSR_READ_1(l, RGE_IDR2); in rge_init()
182 en[3] = CSR_READ_1(l, RGE_IDR3); in rge_init()
183 en[4] = CSR_READ_1(l, RGE_IDR4); in rge_init()
184 en[5] = CSR_READ_1(l, RGE_IDR5); in rge_init()
195 val = CSR_READ_1(l, RGE_PHYSR); in rge_init()
Dstg.c42 #define CSR_READ_1(l, r) in8((l)->csr+(r)) macro
184 en[i] = CSR_READ_1(l, STGE_StationAddress0 + i); in stg_init()
255 reg = CSR_READ_1(l, STGE_PhyCtrl); in stg_init()
403 data |= !!(CSR_READ_1(l, STGE_PhyCtrl) & PC_MgmtData); in mii_read()
445 l->phyctrl_saved = CSR_READ_1(l, STGE_PhyCtrl) & in mii_initphy()
Dfxp.c90 #define CSR_READ_1(l, r) in8((l)->iobase+(r)) macro
377 ruscus = CSR_READ_1(l, FXP_CSR_SCB_RUSCUS); in fxp_recv()
504 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --loop > 0) in fxp_scb_wait()
Dskg.c47 #define CSR_READ_1(l, r) in8((l)->csr+(r)) macro
239 en[i] = CSR_READ_1(l, SK_MAC0 + i); in skg_init()
/netbsd/src/sys/dev/ic/
Dcom.c137 #define CSR_READ_1(r, o) \ macro
485 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || in com_probe_subr()
486 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) in com_probe_subr()
681 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) in com_attach_subr()
683 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) in com_attach_subr()
702 lcr = CSR_READ_1(regsp, COM_REG_LCR); in com_attach_subr()
705 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { in com_attach_subr()
708 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { in com_attach_subr()
740 lcr = CSR_READ_1(regsp, COM_REG_LCR); in com_attach_subr()
745 iir1 = CSR_READ_1(regsp, COM_REG_IIR); in com_attach_subr()
[all …]
Drtl81x9.c147 CSR_READ_1(sc, RTK_EECMD) | (x))
151 CSR_READ_1(sc, RTK_EECMD) & ~(x))
210 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) in rtk_read_eeprom()
230 CSR_READ_1(sc, RTK_MII) | (x))
234 CSR_READ_1(sc, RTK_MII) & ~(x))
604 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) in rtk_reset()
934 while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { in rtk_rxeof()
Dwivar.h246 #define CSR_READ_1(sc, reg) \ macro
268 #define CSR_READ_1(sc, reg) \ macro
Drtl8169.c243 *val = CSR_READ_1(sc, RTK_GMEDIASTAT); in re_gmii_readreg()
341 *val = CSR_READ_1(sc, RTK_MEDIASTAT); in re_miibus_readreg()
429 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) in re_reset()
747 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); in re_attach()
774 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); in re_attach()
779 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80); in re_attach()
2052 switch (CSR_READ_1(sc, RTK_CFG2_BUSFREQ) & 0x7) { in re_init()
Drtl81x9var.h289 #define CSR_READ_1(sc, reg) \ macro
Di82557.c233 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) in fxp_scb_wait()
1086 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); in fxp_intr()
1094 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { in fxp_intr()
1535 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { in fxp_tick()
2282 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == in fxp_mc_setup()
Di82557var.h352 #define CSR_READ_1(sc, reg) \ macro
/netbsd/src/sys/dev/pci/
Dif_vge.c271 #define CSR_READ_1(sc, reg) \ macro
275 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x))
282 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x))
387 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) in vge_read_eeprom()
415 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) in vge_miipoll_stop()
437 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) in vge_miipoll_start()
455 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) in vge_miipoll_start()
473 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) in vge_miibus_readreg()
488 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) in vge_miibus_readreg()
511 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) in vge_miibus_writereg()
[all …]
Dif_vr.c297 #define CSR_READ_1(sc, reg) \ macro
330 CSR_READ_1(sc, reg) | (x))
334 CSR_READ_1(sc, reg) & ~(x))
375 return (CSR_READ_1(sc, VR_MIICMD)); in vr_mii_bitbang_read()
471 rxfilt = CSR_READ_1(sc, VR_RXCFG); in vr_setmulti()
1603 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i)); in vr_attach()
1610 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); in vr_attach()
Dif_ipwreg.h313 #define CSR_READ_1(sc, reg) \ macro
Dif_stge.c234 #define CSR_READ_1(_sc, reg) \ macro
628 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & in stge_attach()
2028 return (CSR_READ_1(sc, STGE_PhyCtrl)); in stge_mii_bitbang_read()
Dif_iwireg.h533 #define CSR_READ_1(sc, reg) \ macro
Dif_ipw.c139 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); in MEM_READ_1()
2287 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); in ipw_read_mem_1()
/netbsd/src/sys/dev/sdmmc/
Dsbt.c39 #define CSR_READ_1(sc, reg) sdmmc_io_read_1((sc)->sc_sf, (reg)) macro
331 status = CSR_READ_1(sc, SBT_REG_ISTAT); in sbt_intr()
/netbsd/src/sys/arch/evbarm/ixm1200/
Dnappi_nppb.c58 #define CSR_READ_1(sc, reg) \ macro
/netbsd/src/sys/arch/arm/xscale/
Dpxa2x0_mci.c145 #define CSR_READ_1(sc, reg) \ macro
980 *cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO); in pxamci_intr_data()
/netbsd/src/sys/arch/arm/imx/
Dimxuart.c1741 msr = CSR_READ_1(regsp, IMXUART_REG_MSR); in imxuintr()
2399 (void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR); in imxuart_suspend()

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