1 /* $NetBSD: bcm53xx_reg.h,v 1.20 2024/02/16 15:11:17 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_BROADCOM_BCM53XX_REG_H_ 33 #define _ARM_BROADCOM_BCM53XX_REG_H_ 34 35 /* 36 * 0x0000_0000..0x07ff_ffff 128MB DDR2/3 DRAM Memory Region (dual map) 37 * 0x0800_0000..0x0fff_ffff 128MB PCIe 0 Address Match Region 38 * 0x1800_0000..0x180f_ffff 1MB Core Register Region 39 * 0x1810_0000..0x181f_ffff 1MB IDM Register Region 40 * 0x1900_0000..0x190f_ffff 1MB ARMcore (CORTEX-A9) Register Region 41 * 0x1c00_0000..0x1dff_ffff 1MB NAND Flash Region 42 * 0x1e00_0000..0x1dff_ffff 1MB Serial Flash Region 43 * 0x4000_0000..0x47ff_ffff 128MB PCIe 1 Address Match Region 44 * 0x4800_0000..0x4fff_ffff 128MB PCIe 2 Address Match Region 45 * 0x8000_0000..0xbfff_ffff 1024MB DDR2/3 DRAM Memory Region 46 * 0xfffd_0000..0xfffe_ffff 128KB Internal Boot ROM Region 47 * 0xffff_0000..0xffff_043f 1088B Internal SKU ROM Region 48 * 0xffff_1000..0xffff_1fff 4KB Enumeration ROM Register Region 49 */ 50 #define BCM53XX_PCIE0_OWIN_PBASE 0x08000000 51 #define BCM53XX_PCIE0_OWIN_SIZE 0x04000000 52 #define BCM53XX_PCIE0_OWIN_MAX 0x08000000 53 54 #define BCM53XX_IOREG_PBASE 0x18000000 55 #define BCM53XX_IOREG_SIZE 0x00200000 56 57 #define BCM53XX_ARMCORE_PBASE 0x19000000 58 #define BCM53XX_ARMCORE_SIZE 0x00100000 59 60 #define BCM53XX_NAND_PBASE 0x1c000000 61 #define BCM53XX_NAND_SIZE 0x01000000 62 63 #define BCM53XX_SPIFLASH_PBASE 0x1d000000 64 #define BCM53XX_SPIFLASH_SIZE 0x01000000 65 66 #define BCM53XX_PCIE1_OWIN_PBASE 0x40000000 67 #define BCM53XX_PCIE1_OWIN_SIZE 0x04000000 68 #define BCM53XX_PCIE1_OWIN_MAX 0x08000000 69 70 #define BCM53XX_PCIE2_OWIN_PBASE 0x48000000 71 #define BCM53XX_PCIE2_OWIN_SIZE 0x04000000 72 #define BCM53XX_PCIE2_OWIN_MAX 0x08000000 73 74 #define BCM53XX_ROM_REGION_PBASE 0xfff00000 75 #define BCM53XX_ROM_REGION_SIZE 0x00100000 76 77 #define BCM53XX_IO_SIZE (BCM53XX_IOREG_SIZE \ 78 + BCM53XX_ARMCORE_SIZE \ 79 + BCM53XX_PCIE0_OWIN_SIZE \ 80 + BCM53XX_PCIE1_OWIN_SIZE \ 81 + BCM53XX_PCIE2_OWIN_SIZE \ 82 + BCM53XX_ROM_REGION_SIZE) 83 84 #define BCM53XX_REF_CLK (25*1000*1000) 85 86 #define CCA_UART_FREQ BCM53XX_REF_CLK 87 88 /* Chip Common A */ 89 #define CCA_MISC_BASE 0x000000 90 #define CCA_MISC_SIZE 0x001000 91 #define CCA_UART0_BASE 0x000300 92 #define CCA_UART1_BASE 0x000400 93 94 /* Chip Common B */ 95 #define CCB_BASE 0x000000 96 #ifdef BCM5301X 97 #define CCB_SIZE 0x030000 98 #define PWM_BASE 0x002000 99 #define MII_BASE 0x003000 100 #define RNG_BASE 0x004000 101 #define TIMER0_BASE 0x005000 102 #define TIMER1_BASE 0x006000 103 #define SRAB_BASE 0x007000 104 #define UART2_BASE 0x008000 105 #define SMBUS1_BASE 0x009000 106 107 #define CRU_BASE 0x00b000 108 #define DMU_BASE 0x00c000 109 #elif defined(BCM563XX) 110 #define CCB_SIZE 0x040000 111 #define GPIO_BASE 0x030000 112 #define PWM_BASE 0x031000 113 #define MII_BASE 0x032000 114 #define RNG_BASE 0x033000 115 #define TIMER0_BASE 0x034000 116 #define TIMER1_BASE 0x035000 117 #define UART2_BASE 0x037000 118 #define SMBUS0_BASE 0x038000 119 #define WDT_BASE 0x039000 120 #define PKA_BASE 0x03a000 121 #define SMBUS1_BASE 0x03b000 122 123 #define CRU_BASE 0x03e000 124 #define DMU_BASE 0x03f000 125 #endif 126 127 #define DDR_BASE 0x010000 128 129 #define PCIE0_BASE 0x012000 130 #define PCIE1_BASE 0x013000 131 132 #ifdef BCM5301X 133 #define PCIE2_BASE 0x014000 134 #define SDIO_BASE 0x020000 135 #define EHCI_BASE 0x021000 136 #define OHCI_BASE 0x022000 137 #define GMAC0_BASE 0x024000 138 #define GMAC1_BASE 0x025000 139 #define GMAC2_BASE 0x026000 140 #define GMAC3_BASE 0x027000 141 #define NAND_BASE 0x028000 142 #define QSPI_BASE 0x029000 143 #define I2S_BASE 0x02A000 144 #define DMAC_BASE 0x02C000 145 #endif 146 147 #ifdef BCM563XX 148 #define DMAC_BASE 0x020000 149 #define GMAC0_BASE 0x022000 150 #define GMAC1_BASE 0x023000 151 #define NAND_BASE 0x026000 152 #define QSPI_BASE 0x027000 153 #define EHCI_BASE 0x02A000 154 #define OHCI_BASE 0x02B000 155 #endif 156 157 #define IDM_BASE 0x100000 158 #define IDM_SIZE 0x100000 159 160 /* Chip Common A */ 161 162 #ifdef CCA_PRIVATE 163 164 #define MISC_CHIPID 0x000 165 #define CHIPID_REV __BITS(19,16) 166 #define CHIPID_ID __BITS(15,0) 167 #define ID_BCM53010 0xcf12 // 53010 168 #define ID_BCM53011 0xcf13 // 53011 169 #define ID_BCM53012 0xcf14 // 53012 170 #define ID_BCM53013 0xcf15 // 53013 171 #define ID_BCM56340 0xdc14 // 56340 172 173 #define MISC_CAPABILITY 0x004 174 #define CAPABILITY_JTAG_PRESENT __BIT(22) 175 #define CAPABILITY_UART_CLKSEL __BITS(4,3) 176 #define UART_CLKSEL_REFCLK 0 177 #define UART_CLKSEL_INTCLK 1 178 /* 2 & 3 are reserved */ 179 #define CAPABILITY_BIG_ENDIAN __BIT(2) 180 #define CAPABILITY_UART_COUNT __BITS(1,0) 181 182 #define MISC_CORECTL 0x008 183 #define CORECTL_UART_CLK_EN __BIT(3) 184 #define CORECTL_GPIO_ASYNC_INT_EN __BIT(2) 185 #define CORECTL_UART_CLK_OVERRIDE __BIT(0) 186 187 #define MISC_INTSTATUS 0x020 188 #define INTSTATUS_WDRESET __BIT(31) // WO2C 189 #define INTSTATUS_UARTINT __BIT(6) // RO 190 #define INTSTATUS_GPIOINT __BIT(0) // RO 191 192 #define MISC_INTMASK 0x024 193 #define INTMASK_UARTINT __BIT(6) // 1 = enabled 194 #define INTMASK_GPIOINT __BIT(0) // 1 = enabled 195 196 /* Only bits [23:0] are used in the GPIO registers */ 197 #define GPIO_INPUT 0x060 // RO 198 #define GPIO_OUT 0x064 199 #define GPIO_OUTEN 0x068 200 #define GPIO_INTPOLARITY 0x070 // 1 = active low 201 #define GPIO_INTMASK 0x074 // 1 = enabled (level) 202 #define GPIO_EVENT 0x078 // W1C, 1 = edge seen 203 #define GPIO_EVENT_INTMASK 0x07c // 1 = enabled (edge) 204 #define GPIO_EVENT_INTPOLARITY 0x084 // 1 = falling 205 #define GPIO_TIMER_VAL 0x088 206 #define TIMERVAL_ONCOUNT __BITS(31,16) 207 #define TIMERVAL_OFFCOUNT __BITS(15,0) 208 #define GPIO_TIMER_OUTMASK 0x08c 209 #define GPIO_DEBUG_SEL 0x0a8 210 211 #define MISC_WATCHDOG 0x080 // 0 disables, 1 resets 212 213 #define MISC_CLKDIV 0x0a4 214 #define CLKDIV_JTAG_MASTER_CLKDIV __BITS(13,9) 215 #define CLKDIV_UART_CLKDIV __BITS(7,1) 216 217 #define MISC_CAPABILITY2 0x0ac 218 #define CAPABILITY2_GSIO_PRESENT __BIT(1) // SPI exists 219 220 #define MISC_GSIOCTL 0x0e4 221 #define GSIOCTL_STARTBUSY __BIT(31) 222 #define GSIOCTL_GSIOMODE __BIT(30) // 0 = SPI 223 #define GSIOCTL_ERROR __BIT(23) 224 #define GSIOCTL_BIGENDIAN __BIT(22) 225 #define GSIOCTL_GSIOGO __BIT(21) 226 #define GSIOCTL_NUM_DATABYTES __BITS(17,16) // actual is + 1 227 #define GSIOCTL_NUM_WAITCYCLES __BITS(15,14) // actual is + 1 228 #define GSIOCTL_NUM_ADDRESSBYTES __BITS(13,12) // actual is + 1 229 #define GSIOCTL_GSIOCODE __BITS(10,8) 230 #define GSIOCODE_OP_RD1DATA 0 231 #define GSIOCODE_OP_WRADDR_RDADDR 1 232 #define GSIOCODE_OP_WRADDR_XFRDATA 2 233 #define GSIOCODE_OP_WRADDR_WAIT_XFRDATA 3 234 #define GSIOCODE_XFRDATA 4 235 #define GSIOCTL_GSIOOP __BITS(7,0) 236 237 #define MISC_GSIOADDRESS 0x0e8 238 #define MISC_GSIODATA 0x0ec 239 240 #define MISC_CLKDIV2 0x0f0 241 #define CLKDIV2_GSIODIV __BITS(20,5) 242 243 #define MISC_EROM_PTR_OFFSET 0x0fc 244 245 #endif /* CCA_PRIVATE */ 246 247 /* 248 * UART0 & 1 use the standard 16550 register layout (normal 1 byte stride) 249 * and have 64-byte FIFOs 250 */ 251 252 /* TIMER0 & 1 are implemented by the dtimer driver */ 253 254 #define TIMER_FREQ BCM53XX_REF_CLK 255 256 #ifdef SRAB_PRIVATE 257 #define SRAB_CMDSTAT 0x002c 258 #define SRA_PAGE __BITS(31,24) 259 #define SRA_OFFSET __BITS(23,16) 260 #define SRA_PAGEOFFSET __BITS(31,16) 261 #define SRA_RST __BIT(2) 262 #define SRA_WRITE __BIT(1) 263 #define SRA_GORDYN __BIT(0) 264 #define SRAB_WDH 0x0030 265 #define SRAB_WDL 0x0034 266 #define SRAB_RDH 0x0038 267 #define SRAB_RDL 0x003c 268 #endif 269 270 #ifdef MII_PRIVATE 271 #define MII_INTERNAL 0x0038003 /* internal phy bitmask */ 272 #define MIIMGT 0x000 273 #define MIIMGT_BYP __BIT(10) 274 #define MIIMGT_EXT __BIT(9) 275 #define MIIMGT_BSY __BIT(8) 276 #define MIIMGT_PRE __BIT(7) 277 #define MIIMGT_MDCDIV __BITS(6,0) 278 #define MIICMD 0x004 279 #define MIICMD_SB __BITS(31,30) 280 #define MIICMD_SB_DEF __SHIFTIN(1, MIICMD_SB) 281 #define MIICMD_OP __BITS(29,28) 282 #define MIICMD_OP_RD __SHIFTIN(2, MIICMD_OP) 283 #define MIICMD_OP_WR __SHIFTIN(1, MIICMD_OP) 284 #define MIICMD_PHY __BITS(27,23) 285 #define MIICMD_REG __BITS(22,18) 286 #define MIICMD_TA __BITS(17,16) 287 #define MIICMD_TA_DEF __SHIFTIN(2, MIICMD_TA) 288 #define MIICMD_DATA __BITS(15,0) 289 290 #define MIICMD_RD_DEF (MIICMD_SB_DEF|MIICMD_OP_RD|MIICMD_TA_DEF) 291 #define MIICMD_WR_DEF (MIICMD_SB_DEF|MIICMD_OP_WR|MIICMD_TA_DEF) 292 #define MIICMD__PHYREG(p,r) (__SHIFTIN(p,MIICMD_PHY)|__SHIFTIN(r,MIICMD_REG)) 293 #define MIICMD_RD(p,r) (MIICMD_RD_DEF|MIICMD__PHYREG((p),(r))) 294 #define MIICMD_WR(p,r,v) (MIICMD_WR_DEF|MIICMD__PHYREG((p),(r))|(v)) 295 #endif /* MII_PRIVATE */ 296 297 #ifdef RNG_PRIVATE 298 #define RNG_CTRL 0x000 299 #define RNG_COMBLK2_OSC_DIS __BITS(27,22) 300 #define RNG_COMBLK1_OSC_DIS __BITS(21,16) 301 #define RNG_ICLK_BYP_DIV_CNT __BITS(15,8) 302 #define RNG_JCLK_BYP_SRC __BIT(5) 303 #define RNG_JCLK_BYP_SEL __BIT(4) 304 #define RNG_RBG2X __BIT(1) 305 #define RNG_RBGEN __BIT(0) 306 #define RNG_STATUS 0x004 307 #define RNG_VAL __BITS(31,24) 308 #define RNG_WARM_CNT __BITS(19,0) 309 310 #define RNG_DATA 0x008 311 #define RNG_FF_THRESHOLD 0x00c 312 #define RNG_INT_MASK 0x010 313 #define RNG_INT_OFF __BIT(0) 314 #endif /* RNG_PRIVATE */ 315 316 #ifdef UART2_PRIVATE 317 /* 318 * UART2 (ChipCommonB) uses a 4-byte stride and 16-byte FIFO. 319 * Its frequency is the APB clock. 320 */ 321 #define UART2_LPDLL 0x020 322 #define UART2_LPDLH 0x024 323 #endif 324 325 #ifdef CRU_PRIVATE 326 327 #define CRU_CONTROL 0x000 328 #define CRUCTL_QSPI_CLK_SEL __BITS(2,1) 329 #define QSPI_CLK_25MHZ 0 // iproc_ref_clk 330 #define QSPI_CLK_50MHZ 1 // iproc_sdio_clk / 4 331 #define QSPI_CLK_31dot25MHZ 2 // iproc_clk250 / 8 332 #define QSPI_CLK_62dot5MHZ 3 // iproc_clk250 / 4 333 #define CRUCTL_SW_RESET __BIT(0) 334 335 #define CRU_GENPLL_CONTROL5 0x1154 336 #define GENPLL_CONTROL5_NDIV_INT __BITS(29,20) // = (n ? n : 1024) 337 #define GENPLL_CONTROL5_NDIV_FRAC __BITS(19,0) // = 1 / n 338 #define CRU_GENPLL_CONTROL6 0x1158 339 #define GENPLL_CONTROL6_PDIV __BITS(26,24) // = (n ? n : 8) 340 #define GENPLL_CONTROL6_CH0_MDIV __BITS(23,16) // = (n ? n : 256), clk_mac 341 #define GENPLL_CONTROL6_CH1_MDIV __BITS(15,8) // = (n ? n : 256), clk_robo 342 #define GENPLL_CONTROL6_CH2_MDIV __BITS(7,0) // = (n ? n : 256), clf_usb2 343 #define CRU_GENPLL_CONTROL7 0x115c 344 #define GENPLL_CONTROL7_CH3_MDIV __BITS(23,16) // = (n ? n : 256), clk_iproc 345 346 #define USB2_REF_CLK (1920*1000*1000) 347 #define CRU_USB2_CONTROL 0x1164 348 #define USB2_CONTROL_KA __BITS(24,22) 349 #define USB2_CONTROL_KI __BITS(31,19) 350 #define USB2_CONTROL_KP __BITS(18,15) 351 #define USB2_CONTROL_PDIV __BITS(14,12) // = (n ? n : 8) 352 #define USB2_CONTROL_NDIV_INT __BITS(11,2) // = (n ? n : 1024) 353 #define USB2_CONTROL_PLL_PCIEUSB3_RESET __BIT(1) // inverted 1=normal 354 #define USB2_CONTROL_PLL_USB2_RESET __BIT(0) // inverted 1=normal 355 356 #define CRU_CLKSET_KEY 0x1180 357 #define CRU_CLKSET_KEY_MAGIC 0xea68 358 359 #define CRU_GPIO_SELECT 0x11c0 // CRU GPIO Select 360 #define CRU_GPIO_DRIVE_SEL2 0x11c4 361 #define CRU_GPIO_DRIVE_SEL1 0x11c8 362 #define CRU_GPIO_DRIVE_SEL0 0x11cc 363 #define CRU_GPIO_INPUT_DISABLE 0x11d0 364 #define CRU_GPIO_HYSTERESIS 0x11d4 365 #define CRU_GPIO_SLEW_RATE 0x11d8 366 #define CRU_GPIO_PULL_UP 0x11dc 367 #define CRU_GPIO_PULL_DOWN 0x11e0 368 369 #define CRU_STRAPS_CONTROL 0x12a0 370 #define STRAP_BOOT_DEV __BITS(17,16) 371 #define STRAP_NAND_TYPE __BITS(15,12) 372 #define STRAP_NAND_PAGE __BITS(11,10) 373 #define STRAP_DDR3 __BIT(9) 374 #define STRAP_P5_VOLT_15 __BIT(8) 375 #define STRAP_P5_MODE __BITS(7,6) 376 #define STRAP_PCIE0_MODE __BIT(5) 377 #define STRAP_USB3_SEL __BIT(4) 378 #define STRAP_EX_EXTCLK __BIT(3) 379 #define STRAP_HW_FWDG_EN __BIT(2) 380 #define STRAP_LED_SERIAL_MODE __BIT(1) 381 #define STRAP_BISR_BYPASS_AUTOLOAD __BIT(0) 382 383 #endif /* CRU_PRIVATE */ 384 385 #ifdef DMU_PRIVATE 386 387 #define DMU_LCPLL_CONTROL0 0x100 388 #define DMU_LCPLL_CONTROL1 0x104 389 #define LCPLL_CONTROL1_PDIV __BITS(30,28) // = (n ? n : 8) 390 #define LCPLL_CONTROL1_NDIV_INT __BITS(27,20) // = (n ? n : 256) 391 #define LCPLL_CONTROL1_NDIV_FRAC __BITS(19,0) // = 1 / n 392 /* 393 * SYS_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref) 394 */ 395 #define DMU_LCPLL_CONTROL2 0x108 396 #define LCPLL_CONTROL2_CH0_MDIV __BITS(31,24) // = (n ? n : 256), clk_pcie_ref 397 #define LCPLL_CONTROL2_CH1_MDIV __BITS(23,16) // = (n ? n : 256), clk_sdio 398 #define LCPLL_CONTROL2_CH2_MDIV __BITS(15,8) // = (n ? n : 256), clk_ddr 399 #define LCPLL_CONTROL2_CH3_MDIV __BITS(7,0) // = (n ? n : 256), clf_dft 400 401 #define DMU_CRU_RESET 0x200 402 #define DMU_CRU_RESET_IPROC __BIT(1) 403 #define DMU_CRU_RESET_CMICD __BIT(0) 404 405 #endif /* DMU_PRIVATE */ 406 407 #ifdef DDR_PRIVATE 408 /* 409 * DDR CTL register has such inspired names. 410 */ 411 #define DDR_CTL_01 0x004 412 #define CTL_01_MAX_CHIP_SEL __BITS(18,16) // not documented as such 413 #define CTL_01_MAX_COL __BITS(11,8) 414 #define CTL_01_MAX_ROW __BITS(4,0) 415 416 #define DDR_CTL_82 0x148 417 #define CTL_82_COL_DIFF __BITS(26,24) 418 #define CTL_82_ROW_DIFF __BITS(18,16) 419 #define CTL_82_BANK_DIFF __BITS(9,8) 420 #define CTL_82_ZQCS_ROTATE __BIT(0) 421 422 #define DDR_CTL_86 0x158 423 #define CTL_86_CS_MAP __BITS(27,24) 424 #define CTL_86_INHIBIT_DRAM_CMD __BIT(16) 425 #define CTL_86_DIS_RD_INTRLV __BIT(8) 426 #define CTL_86_NUM_QENT_ACT_DIS __BITS(2,0) 427 428 #define DDR_CTL_87 0x15c 429 #define CTL_87_IN_ORDER_ACCEPT __BIT(24) 430 #define CTL_87_Q_FULLNESS __BITS(18,16) 431 #define CTL_87_REDUC __BIT(8) 432 #define CTL_87_BURST_ON_FLY_BIT __BITS(3,0) 433 434 #define DDR_PHY_CTL_PLL_STATUS 0x810 435 #define PLL_STATUS_LOCK_LOST __BIT(26) 436 #define PLL_STATUS_MHZ __BITS(25,14) 437 #define PLL_STATUS_CLOCKING_4X __BIT(13) 438 #define PLL_STATUS_STATUS __BITS(12,1) 439 #define PLL_STATUS_LOCK __BIT(0) 440 441 #define DDR_PHY_CTL_PLL_DIVIDERS 0x81c 442 #define PLL_DIVIDERS_POST_DIV __BITS(13,11) 443 #define PLL_DIVIDERS_PDIV __BITS(10,8) // 4x: (n ? n : 8), n = n - 4, 4x 444 #define PLL_DIVIDERS_NDIV __BITS(7,0) 445 446 #endif /* DDR_PRIVATE */ 447 448 #ifdef PCIE_PRIVATE 449 450 #define PCIE_CLK_CONTROL 0x000 451 452 #define PCIE_RC_AXI_CONFIG 0x100 453 #define PCIE_AWCACHE_CONFIG __BITS(17,14) 454 #define PCIE_AWUSER_CONFIG __BITS(13,9) 455 #define PCIE_ARCACHE_CONFIG __BITS(8,5) 456 #define PCIE_ARUSER_CONFIG __BITS(4,0) 457 458 #define PCIE_CFG_IND_ADDR 0x120 459 #define CFG_IND_ADDR_FUNC __BITS(15,13) 460 #define CFG_IND_ADDR_LAYER __BITS(12,11) 461 #define CFG_IND_ADDR_REG __BITS(10,2) 462 #define PCIE_CFG_IND_DATA 0x124 463 #define PCIE_CFG_ADDR 0x1f8 464 #define CFG_ADDR_BUS __BITS(27,20) 465 #define CFG_ADDR_DEV __BITS(19,15) 466 #define CFG_ADDR_FUNC __BITS(14,12) 467 #define CFG_ADDR_REG __BITS(11,2) 468 #define CFG_ADDR_TYPE __BITS(1,0) 469 #define CFG_ADDR_TYPE0 __SHIFTIN(0, CFG_ADDR_TYPE) 470 #define CFG_ADDR_TYPE1 __SHIFTIN(1, CFG_ADDR_TYPE) 471 #define PCIE_CFG_DATA 0x1fc 472 #define PCIE_EQ_PAGE 0x200 473 #define PCIE_MSI_PAGE 0x204 474 #define PCIE_MSI_INTR_EN 0x208 475 #define PCIE_MSI_CTRL_0 0x210 476 #define PCIE_MSI_CTRL_1 0x214 477 #define PCIE_MSI_CTRL_2 0x218 478 #define PCIE_MSI_CTRL_3 0x21c 479 #define PCIE_MSI_CTRL_4 0x220 480 #define PCIE_MSI_CTRL_5 0x224 481 #define PCIE_SYS_EQ_HEAD_0 0x250 482 #define PCIE_SYS_EQ_TAIL_0 0x254 483 #define PCIE_SYS_EQ_HEAD_1 0x258 484 #define PCIE_SYS_EQ_TAIL_1 0x25c 485 #define PCIE_SYS_EQ_HEAD_2 0x260 486 #define PCIE_SYS_EQ_TAIL_2 0x264 487 #define PCIE_SYS_EQ_HEAD_3 0x268 488 #define PCIE_SYS_EQ_TAIL_3 0x26c 489 #define PCIE_SYS_EQ_HEAD_4 0x270 490 #define PCIE_SYS_EQ_TAIL_4 0x274 491 #define PCIE_SYS_EQ_HEAD_5 0x278 492 #define PCIE_SYS_EQ_TAIL_5 0x27c 493 #define PCIE_SYS_RC_INTX_EN 0x330 494 #define PCIE_SYS_RC_INTX_CSR 0x334 495 496 #define PCIE_CFG000_BASE 0x400 497 498 #define PCIE_FUNC0_IMAP0_0 0xc00 499 #define PCIE_FUNC0_IMAP0_1 0xc04 500 #define PCIE_FUNC0_IMAP0_2 0xc08 501 #define PCIE_FUNC0_IMAP0_3 0xc0c 502 #define PCIE_FUNC0_IMAP0_4 0xc10 503 #define PCIE_FUNC0_IMAP0_5 0xc14 504 #define PCIE_FUNC0_IMAP0_6 0xc18 505 #define PCIE_FUNC0_IMAP0_7 0xc1c 506 507 #define PCIE_FUNC0_IMAP1 0xc80 508 #define PCIE_FUNC1_IMAP1 0xc88 509 #define PCIE_FUNC0_IMAP2 0xcc0 510 #define PCIE_FUNC1_IMAP2 0xcc8 511 512 #define PCIE_IARR_0_LOWER 0xd00 513 #define PCIE_IARR_0_UPPER 0xd04 514 #define PCIE_IARR_1_LOWER 0xd08 515 #define PCIE_IARR_1_UPPER 0xd0c 516 #define PCIE_IARR_2_LOWER 0xd10 517 #define PCIE_IARR_2_UPPER 0xd14 518 519 #define PCIE_OARR_0 0xd20 520 #define PCIE_OARR_1 0xd28 521 522 #define PCIE_OARR_ADDR __BITS(31,26) 523 524 #define PCIE_OMAP_0_LOWER 0xd40 525 #define PCIE_OMAP_0_UPPER 0xd44 526 #define PCIE_OMAP_1_LOWER 0xd48 527 #define PCIE_OMAP_1_UPPER 0xd4c 528 529 #define PCIE_OMAP_ADDRL __BITS(31,26) 530 531 #define PCIE_FUNC1_IARR_1_SIZE 0xd58 532 #define PCIE_FUNC1_IARR_2_SIZE 0xd5c 533 534 #define PCIE_MEM_CONTROL 0xf00 535 #define PCIE_MEM_ECC_ERR_LOG_0 0xf04 536 #define PCIE_MEM_ECC_ERR_LOG_1 0xf08 537 538 #define PCIE_LINK_STATUS 0xf0c 539 #define PCIE_PHYLINKUP __BIT(3) 540 #define PCIE_DL_ACTIVE __BIT(2) 541 #define PCIE_RX_LOS_TIMEOUT __BIT(1) 542 #define PCIE_LINK_IN_L1 __BIT(0) 543 #define PCIE_STRAP_STATUS 0xf10 544 #define STRAP_PCIE_REPLAY_BUF_TM __BITS(8,4) 545 #define STRAP_PCIE_USER_FOR_CE_GEN1 __BIT(3) 546 #define STRAP_PCIE_USER_FOR_CE_1LANE __BIT(2) 547 #define STRAP_PCIE_IF_ENABLE __BIT(1) 548 #define STRAP_PCIE_USER_RC_MODE __BIT(0) 549 #define PCIE_RESET_STATUS 0xf14 550 551 #define PCIE_RESET_ENABLE_IN_PCIE_LINK_DOWN 0xf18 552 553 #define PCIE_MISC_INTR_EN 0xf1c 554 #define PCIE_TX_DEBUG_CFG 0xf20 555 #define PCIE_ERROR_INTR_EN 0xf30 556 #define PCIE_ERROR_INTR_CLR 0xf34 557 #define PCIE_ERROR_INTR_STS 0xf38 558 559 560 // PCIE_SYS_MSI_INTR_EN 561 #define MSI_INTR_EN_EQ_5 __BIT(5) 562 #define MSI_INTR_EN_EQ_4 __BIT(4) 563 #define MSI_INTR_EN_EQ_3 __BIT(3) 564 #define MSI_INTR_EN_EQ_2 __BIT(2) 565 #define MSI_INTR_EN_EQ_1 __BIT(1) 566 #define MSI_INTR_EN_EQ_0 __BIT(0) 567 568 // PCIE_SYS_MSI_CTRL<n> 569 #define INT_N_DELAY __BITS(9,6) 570 #define INT_N_EVENT __BITS(1,1) 571 #define EQ_ENABLE __BIT(0) 572 573 // PCIE_SYS_EQ_HEAD<n> 574 #define HEAD_PTR __BITS(5,0) 575 576 // PCIE_SYS_EQ_TAIL<n> 577 #define EQ_OVERFLOW __BIT(6) 578 #define TAIL_PTR __BITS(5,0) 579 580 // PCIE_SYS_RC_INTRX_EN 581 #define RC_EN_INTD __BIT(3) 582 #define RC_EN_INTC __BIT(2) 583 #define RC_EN_INTB __BIT(1) 584 #define RC_EN_INTA __BIT(0) 585 586 // PCIE_SYS_RC_INTRX_CSR 587 #define RC_INTD __BIT(3) 588 #define RC_INTC __BIT(2) 589 #define RC_INTB __BIT(1) 590 #define RC_INTA __BIT(0) 591 592 // PCIE_IARR_0_LOWER / UPPER 593 #define IARR0_ADDR __BIT(31,15) 594 #define IARR0_VALID __BIT(0) 595 596 // PCIE_IARR_1_LOWER / UPPER 597 #define IARR1_ADDR __BIT(31,20) 598 #define IARR1_SIZE __BIT(7,0) 599 600 // PCIE_IARR_2_LOWER / UPPER 601 #define IARR2_ADDR __BIT(31,20) 602 #define IARR2_SIZE __BIT(7,0) 603 604 // PCIE_MISC_INTR_EN 605 #define INTR_EN_PCIE_ERR_ATTN __BIT(2) 606 #define INTR_EN_PAXB_ECC_2B_ATTN __BIT(1) 607 #define INTR_EN_PCIE_IN_WAKE_B __BIT(0) 608 609 // PCIE_ERR_INTR_{EN,CLR,STS} 610 #define PCIE_OVERFLOW_UNDERFLOW_INTR __BIT(10) 611 #define PCIE_AXI_MASTER_RRESP_SLV_ERR_INTR __BIT(9) 612 #define PCIE_AXI_MASTER_RRESP_DECERR_INTR __BIT(8) 613 #define PCIE_ECRC_ERR_INTR __BIT(7) 614 #define PCIE_CMPL_TIMEROUT_INTR __BIT(6) 615 #define PCIE_ERR_ATTN_INTR __BIT(5) 616 #define PCIE_IN_WAKE_B_INTR __BIT(4) 617 #define PCIE_REPLAY_BUF_2B_ECC_ERR_INTR __BIT(3) 618 #define PCIE_RD_CMPL_BUF_1_2B_ECC_ERR_INTR __BIT(2) 619 #define PCIE_RD_CMPL_BUF_0_2B_ECC_ERR_INTR __BIT(1) 620 #define PCIE_WR_DATA_BUF_2B_ECC_ERR_INTR __BIT(0) 621 622 #define REGS_DEVICE_CAPACITY 0x04d4 623 #define REGS_LINK_CAPACITY 0x03dc 624 #define REGS_TL_CONTROL_0 0x0800 625 #define REGS_DL_STATUS 0x1048 626 627 #endif /* PCIE_PRIVATE */ 628 629 #define ARMCORE_SCU_BASE 0x20000 /* CBAR is 19020000 */ 630 #define ARMCORE_L2C_BASE 0x22000 631 632 #ifdef ARMCORE_PRIVATE 633 634 #define ARMCORE_CLK_POLICY_FREQ 0x008 635 #define CLK_POLICY_FREQ_PRIVED __BIT(31) 636 #define CLK_POLICY_FREQ_POLICY3 __BITS(26,24) 637 #define CLK_POLICY_FREQ_POLICY2 __BITS(18,16) 638 #define CLK_POLICY_FREQ_POLICY1 __BITS(10,8) 639 #define CLK_POLICY_FREQ_POLICY0 __BITS(2,0) 640 #define CLK_POLICY_REF_CLK 0 // 25 MHZ 641 #define CLK_POLICY_SYS_CLK 1 // sys clk (200MHZ) 642 #define CLK_POLICY_ARM_PLL_CH0 6 // slow clock 643 #define CLK_POLICY_ARM_PLL_CH1 7 // fast clock 644 645 #define ARMCORE_CLK_APB_DIV 0xa10 646 #define CLK_APB_DIV_PRIVED __BIT(31) 647 #define CLK_APB_DIV_VALUE __BITS(1,0) // n = n + 1 648 649 #define ARMCORE_CLK_APB_DIV_TRIGGER 0xa10 650 #define CLK_APB_DIV_TRIGGER_PRIVED __BIT(31) 651 #define CLK_APB_DIV_TRIGGER_OVERRIDE __BIT(0) 652 653 #define ARMCORE_CLK_PLLARMA 0xc00 654 #define CLK_PLLARMA_PDIV __BITS(26,24) // = (n ? n : 16(?)) 655 #define CLK_PLLARMA_NDIV_INT __BITS(17,8) // = (n ? n : 1024) 656 657 #define ARMCORE_CLK_PLLARMB 0xc04 658 #define CLK_PLLARMB_NDIV_FRAC __BITS(19,0) // = 1 / n 659 660 #endif 661 662 #ifdef IDM_PRIVATE 663 664 #define IDM_ARMCORE_M0_BASE 0x00000 665 #define IDM_PCIE_M0_BASE 0x01000 666 #define IDM_PCIE_M1_BASE 0x02000 667 #define IDM_PCIE_M2_BASE 0x03000 668 #define IDM_USB3_BASE 0x05000 669 #define IDM_ARMCORE_S1_BASE 0x06000 670 #define IDM_ARMCORE_S0_BASE 0x07000 671 #define IDM_DDR_S1_BASE 0x08000 672 #define IDM_DDR_S2_BASE 0x09000 673 #define IDM_ROM_S0_BASE 0x0d000 674 #define IDM_AMAC0_BASE 0x10000 675 #define IDM_AMAC1_BASE 0x11000 676 #define IDM_AMAC2_BASE 0x12000 677 #define IDM_AMAC3_BASE 0x13000 678 #define IDM_DMAC_M0_BASE 0x14000 679 #define IDM_USB2_BASE 0x15000 680 #define IDM_SDIO_BASE 0x16000 681 #define IDM_I2S_M0_BASE 0x17000 682 #define IDM_A9JTAG_M0_BASE 0x18000 683 #ifdef BCM5301X 684 #define IDM_NAND_BASE 0x1a000 685 #define IDM_QSPI_BASE 0x1b000 686 #endif 687 #ifdef BCM563XX 688 #define IDM_NAND_BASE 0x1b000 689 #define IDM_QSPI_BASE 0x1c000 690 #endif 691 #define IDM_APBX_BASE 0x21000 692 693 #define IDM_IO_CONTROL_DIRECT 0x0408 694 #define IDM_IO_STATUS 0x0500 695 #define IDM_RESET_CONTROL 0x0800 696 #define IDM_RESET_STATUS 0x0804 697 #define IDM_INTERRUPT_STATUS 0x0a00 698 699 #define IO_CONTROL_DIRECT_ARUSER __BITS(29,25) 700 #define IO_CONTROL_DIRECT_AWUSER __BITS(24,20) 701 #define IO_CONTROL_DIRECT_ARCACHE __BITS(19,16) 702 #define IO_CONTROL_DIRECT_AWCACHE __BITS(10,7) 703 #define AXCACHE_WA __BIT(3) 704 #define AXCACHE_RA __BIT(2) 705 #define AXCACHE_C __BIT(1) 706 #define AXCACHE_B __BIT(0) 707 #define IO_CONTROL_DIRECT_UARTCLKSEL __BIT(17) 708 #define IO_CONTROL_DIRECT_CLK_250_SEL __BIT(6) 709 #define IO_CONTROL_DIRECT_DIRECT_GMII_MODE __BIT(5) 710 #define IO_CONTROL_DIRECT_TX_CLK_OUT_INVERT_EN __BIT(4) 711 #define IO_CONTROL_DIRECT_DEST_SYNC_MODE_EN __BIT(3) 712 #define IO_CONTROL_DIRECT_SOURCE_SYNC_MODE_EN __BIT(2) 713 #define IO_CONTROL_DIRECT_CLK_GATING_EN __BIT(0) 714 715 #define RESET_CONTROL_RESET __BIT(0) 716 717 #endif /* IDM_PRIVATE */ 718 719 #ifdef USBH_PRIVATE 720 #define USBH_PHY_CTRL_P0 0x200 721 #define USBH_PHY_CTRL_P1 0x204 722 723 #define USBH_PHY_CTRL_INIT 0x3ff 724 #endif 725 726 #ifdef GMAC_PRIVATE 727 728 struct gmac_txdb { 729 uint32_t txdb_flags; 730 uint32_t txdb_buflen; 731 uint32_t txdb_addrlo; 732 uint32_t txdb_addrhi; 733 }; 734 #define TXDB_FLAG_SF __BIT(31) // Start oF Frame 735 #define TXDB_FLAG_EF __BIT(30) // End oF Frame 736 #define TXDB_FLAG_IC __BIT(29) // Interrupt on Completion 737 #define TXDB_FLAG_ET __BIT(28) // End Of Table 738 739 struct gmac_rxdb { 740 uint32_t rxdb_flags; 741 uint32_t rxdb_buflen; 742 uint32_t rxdb_addrlo; 743 uint32_t rxdb_addrhi; 744 }; 745 #define RXDB_FLAG_SF __BIT(31) // Start oF Frame (ignored) 746 #define RXDB_FLAG_EF __BIT(30) // End oF Frame (ignored) 747 #define RXDB_FLAG_IC __BIT(29) // Interrupt on Completion 748 #define RXDB_FLAG_ET __BIT(28) // End Of Table 749 750 #define RXSTS_FRAMELEN __BITS(15,0) // # of bytes (including padding) 751 #define RXSTS_PKTTYPE __BITS(17,16) 752 #define RXSTS_PKTTYPE_UC 0 // Unicast 753 #define RXSTS_PKTTYPE_MC 1 // Multicast 754 #define RXSTS_PKTTYPE_BC 2 // Broadcast 755 #define RXSTS_VLAN_PRESENT __BIT(18) 756 #define RXSTS_CRC_ERROR __BIT(19) 757 #define RXSTS_OVERSIZED __BIT(20) 758 #define RXSTS_CTF_HIT __BIT(21) 759 #define RXSTS_CTF_ERROR __BIT(22) 760 #define RXSTS_PKT_OVERFLOW __BIT(23) 761 #define RXSTS_DESC_COUNT __BITS(27,24) // # of descriptors - 1 762 763 #define GMAC_DEVCONTROL 0x000 764 #define ENABLE_DEL_G_TXC __BIT(21) 765 #define ENABLE_DEL_G_RXC __BIT(20) 766 #define TXC_DRNG __BITS(19,18) 767 #define RXC_DRNG __BITS(17,16) 768 #define TXQ_FLUSH __BIT(8) 769 #define NWAY_AUTO_POLL_EN __BIT(7) 770 #define FLOW_CTRL_MODE __BITS(6,5) 771 #define MIB_RD_RESET_EN __BIT(4) 772 #define RGMII_LINK_STATUS_SEL __BIT(3) 773 #define CPU_FLOW_CTRL_ON __BIT(2) 774 #define RXQ_OVERFLOW_CTRL_SEL __BIT(1) 775 #define TXARB_STRICT_MODE __BIT(0) 776 #define GMAC_DEVSTATUS 0x004 777 #define GMAC_BISTSTATUS 0x00c 778 #define GMAC_INTSTATUS 0x020 779 #define GMAC_INTMASK 0x024 780 #define TXQECCUNCORRECTED __BIT(31) 781 #define TXQECCCORRECTED __BIT(30) 782 #define RXQECCUNCORRECTED __BIT(29) 783 #define RXQECCCORRECTED __BIT(28) 784 #define XMTINT_3 __BIT(27) 785 #define XMTINT_2 __BIT(26) 786 #define XMTINT_1 __BIT(25) 787 #define XMTINT_0 __BIT(24) 788 #define RCVINT __BIT(16) 789 #define XMTUF __BIT(15) 790 #define RCVFIFOOF __BIT(14) 791 #define RCVDESCUF __BIT(13) 792 #define DESCPROTOERR __BIT(12) 793 #define DATAERR __BIT(11) 794 #define DESCERR __BIT(10) 795 #define INT_SW_LINK_ST_CHG __BIT(8) 796 #define INT_TIMEOUT __BIT(7) 797 #define MIB_TX_INT __BIT(6) 798 #define MIB_RX_INT __BIT(5) 799 #define MDIOINT __BIT(4) 800 #define NWAYLINKSTATINT __BIT(3) 801 #define TXQ_FLUSH_DONEINT __BIT(2) 802 #define MIB_TX_OVERFLOW __BIT(1) 803 #define MIB_RX_OVERFLOW __BIT(0) 804 #define GMAC_GPTIMER 0x028 805 806 #define GMAC_INTRCVLAZY 0x100 807 #define INTRCVLAZY_FRAMECOUNT __BITS(31,24) 808 #define INTRCVLAZY_TIMEOUT __BITS(23,0) 809 #define GMAC_FLOWCNTL_TH 0x104 810 #define GMAC_TXARB_WRR_TH 0x108 811 #define GMAC_GMACIDLE_CNT_TH 0x10c 812 813 #define GMAC_FIFOACCESSADDR 0x120 814 #define GMAC_FIFOACCESSBYTE 0x124 815 #define GMAC_FIFOACCESSDATA 0x128 816 817 #define GMAC_PHYACCESS 0x180 818 #define GMAC_PHYCONTROL 0x188 819 #define GMAC_TXQCONTROL 0x18c 820 #define GMAC_RXQCONTROL 0x190 821 #define GMAC_GPIOSELECT 0x194 822 #define GMAC_GPIOOUTPUTEN 0x198 823 #define GMAC_TXQRXQMEMORYCONTROL 0x1a0 824 #define GMAC_MEMORYECCSTATUS 0x1a4 825 826 #define GMAC_CLOCKCONTROLSTATUS 0x1e0 827 #define GMAC_POWERCONTROL 0x1e8 828 829 #define GMAC_XMTCONTROL 0x200 830 #define XMTCTL_PREFETCH_THRESH __BITS(25,24) 831 #define XMTCTL_PREFETCH_CTL __BITS(23,21) 832 #define XMTCTL_BURSTLEN __BITS(20,18) 833 #define XMTCTL_ADDREXT __BITS(17,16) 834 #define XMTCTL_DMA_ACT_INDEX __BIT(13) 835 #define XMTCTL_PARITY_DIS __BIT(11) 836 #define XMTCTL_OUTSTANDING_READS __BITS(7,6) 837 #define XMTCTL_BURST_ALIGN_EN __BIT(5) 838 #define XMTCTL_DMA_LOOPBACK __BIT(2) 839 #define XMTCTL_SUSPEND __BIT(1) 840 #define XMTCTL_ENABLE __BIT(0) 841 #define GMAC_XMTPTR 0x204 842 #define XMT_LASTDSCR __BITS(11,4) 843 #define GMAC_XMTADDR_LOW 0x208 844 #define GMAC_XMTADDR_HIGH 0x20c 845 #define GMAC_XMTSTATUS0 0x210 846 #define XMTSTATE __BITS(31,28) 847 #define XMTSTATE_DIS 0 848 #define XMTSTATE_ACTIVE 1 849 #define XMTSTATE_IDLE_WAIT 2 850 #define XMTSTATE_STOPPED 3 851 #define XMTSTATE_SUSP_PENDING 4 852 #define XMT_CURRDSCR __BITS(11,4) 853 #define GMAC_XMTSTATUS1 0x214 854 #define XMTERR __BITS(31,28) 855 #define XMT_ACTIVEDSCR __BITS(11,4) 856 #define GMAC_RCVCONTROL 0x220 857 #define RCVCTL_PREFETCH_THRESH __BITS(25,24) 858 #define RCVCTL_PREFETCH_CTL __BITS(23,21) 859 #define RCVCTL_BURSTLEN __BITS(20,18) 860 #define RCVCTL_ADDREXT __BITS(17,16) 861 #define RCVCTL_DMA_ACT_INDEX __BIT(13) 862 #define RCVCTL_PARITY_DIS __BIT(11) 863 #define RCVCTL_OFLOW_CONTINUE __BIT(10) 864 #define RCVCTL_SEPRXHDRDESC __BIT(9) 865 #define RCVCTL_RCVOFFSET __BITS(7,1) 866 #define RCVCTL_ENABLE __BIT(0) 867 #define GMAC_RCVPTR 0x224 868 #define RCVPTR __BITS(11,4) 869 #define GMAC_RCVADDR_LOW 0x228 870 #define GMAC_RCVADDR_HIGH 0x22c 871 #define GMAC_RCVSTATUS0 0x230 872 #define RCVSTATE __BITS(31,28) 873 #define RCVSTATE_DIS 0 874 #define RCVSTATE_ACTIVE 1 875 #define RCVSTATE_IDLE_WAIT 2 876 #define RCVSTATE_STOPPED 3 877 #define RCVSTATE_SUSP_PENDING 4 878 #define RCV_CURRDSCR __BITS(11,4) 879 #define GMAC_RCVSTATUS1 0x234 880 #define RCV_ACTIVEDSCR __BITS(11,4) 881 882 #define GMAC_TX_GD_OCTETS_LO 0x300 883 884 885 #define UNIMAC_IPG_HD_BPG_CNTL 0x804 886 #define UNIMAC_COMMAND_CONFIG 0x808 887 #define RUNT_FILTER_DIS __BIT(30) 888 #define OOB_EFC_EN __BIT(29) 889 #define IGNORE_TX_PAUSE __BIT(28) 890 #define PRBL_ENA __BIT(27) 891 #define RX_ERR_DIS __BIT(26) 892 #define LINE_LOOPBACK __BIT(25) 893 #define NO_LENGTH_CHECK __BIT(24) 894 #define CNTRL_FRM_ENA __BIT(23) 895 #define ENA_EXT_CONFIG __BIT(22) 896 #define EN_INTERNAL_TX_CRS __BIT(21) 897 #define SW_OVERRIDE_RX __BIT(18) 898 #define SW_OVERRIDE_TX __BIT(17) 899 #define MAC_LOOP_CON __BIT(16) 900 #define LOOP_ENA __BIT(15) 901 #define RCS_CORRUPT_URUN_EN __BIT(14) 902 #define SW_RESET __BIT(13) 903 #define OVERFLOW_EN __BIT(12) 904 #define RX_LOW_LATENCY_EN __BIT(11) 905 #define HD_ENA __BIT(10) 906 #define TX_ADDR_INS __BIT(9) 907 #define PAUSE_IGNORE __BIT(8) 908 #define PAUSE_FWD __BIT(7) 909 #define CRC_FWD __BIT(6) 910 #define PAD_EN __BIT(5) 911 #define PROMISC_EN __BIT(4) 912 #define ETH_SPEED __BITS(3,2) 913 #define ETH_SPEED_10 0 914 #define ETH_SPEED_100 1 915 #define ETH_SPEED_1000 2 916 #define ETH_SPEED_2500 3 917 #define RX_ENA __BIT(1) 918 #define TX_ENA __BIT(0) 919 #define UNIMAC_MAC_0 0x80c // bits 16:47 of macaddr 920 #define UNIMAC_MAC_1 0x810 // bits 0:15 of macaddr 921 #define UNIMAC_FRAME_LEN 0x814 922 #define UNIMAC_PAUSE_QUANTA 0x818 923 #define UNIMAC_TX_TS_SEQ_ID 0x83c 924 #define UNIMAC_MAC_MODE 0x844 925 #define UNIMAC_TAG_0 0x848 926 #define UNIMAC_TAG_1 0x84c 927 #define UNIMAC_RX_PAUSE_QUANTA_SCALE 0x850 928 #define UNIMAC_TX_PREAMBLE 0x854 929 #define UNIMAC_TX_IPG_LENGTH 0x85c 930 #define UNIMAC_PRF_XOFF_TIMER 0x860 931 #define UNIMAC_UMAC_EEE_CTRL 0x864 932 #define UNIMAC_MII_EEE_DELAY_ENTRY_TIMER 0x868 933 #define UNIMAC_GMII_EEE_DELAY_ENTRY_TIMER 0x86c 934 #define UNIMAC_UMAC_EEE_REF_COUNT 0x870 935 #define UNIMAC_UMAX_RX_PKT_DROP_STATUS 0x878 936 937 #define UNIMAC_UMAC_SYMMETRIC_IDLE_THRESHOLD 0x87c // RX IDLE threshold for LPI prediction 938 #define UNIMAC_MII_EEE_WAKE_TIMER 0x880 // MII_EEE Wake timer 939 #define UNIMAC_GMII_EEE_WAKE_TIMER 0x884 // GMII_EEE Wake timer 940 #define UNIMAC_UMAC_REV_ID 0x888 // UNIMAC_REV_ID 941 #define UNIMAC_MAC_PFC_TYPE 0xb00 // Programmable ethertype (GNAT 13440) 942 #define UNIMAC_MAC_PFC_OPCODE 0xb04 // Programmable opcode (GNAT 13440) 943 #define UNIMAC_MAC_PFC_DA_0 0xb08 // lower 32 bits of programmable DA for PPP (GNAT 13897) 944 #define UNIMAC_MAC_PFC_DA_1 0xb0c // upper 16 bits of programmable DA for PPP (GNAT 13897) 945 #define UNIMAC_MACSEC_CNTRL 0xb14 // Miscellaneous control for MACSEC (GNAT 11599,11600,12078,12198) 946 #define UNIMAC_TS_STATUS_CNTRL 0xb18 // Timestamp control/status 947 #define UNIMAC_TX_TS_DATA 0xb1c // Transmit Timestamp data 948 #define UNIMAC_PAUSE_CONTROL 0xb30 // PAUSE frame timer control register 949 #define UNIMAC_FLUSH_CONTROL 0xb34 // Flush enable control register 950 #define UNIMAC_RXFIFO_STAT 0xb38 // RXFIFO status register 951 #define UNIMAC_TXFIFO_STAT 0xb3c // TXFIFO status register 952 #define UNIMAC_MAC_PFC_CTRL 0xb40 // PPP control register 953 #define UNIMAC_MAC_PFC_REFRESH_CTRL 0xb44 // PPP refresh control register 954 955 #endif /* GMAC_PRIVATE */ 956 957 #ifdef NAND_PRIVATE 958 959 #define NAND_REVISION 0x0000 // NAND Revision 960 #define NAND_CMD_START 0x0004 // Nand Flash Command Start 961 #define NAND_CMD_EXT_ADDR 0x0008 // Nand Flash Command Extended Address 962 #define NAND_CMD_ADDR 0x000c // Nand Flash Command Address 963 #define NAND_CMD_END_ADDR 0x0010 // Nand Flash Command End Address 964 #define NAND_INTFC_STATUS 0x0014 // Nand Flash Interface Status 965 #define NAND_CS_NAND_SELECT 0x0018 // Nand Flash CS 966 #define NAND_CS_NAND_XOR 0x001c // Nand Flash EBI 967 #define NAND_LL_OP 0x0020 // Nand Flash Low Level Operation 968 #define NAND_MPLANE_BASE_EXT_ADDR 0x0024 // Nand Flash Multiplane base address 969 #define NAND_MPLANE_BASE_ADDR 0x0028 // Nand Flash Multiplane base address 970 #define NAND_ACC_CONTROL_CS0 0x0050 // Nand Flash Access Control 971 #define NAND_CONFIG_CS0 0x0054 // Nand Flash Config 972 #define NAND_TIMING_1_CS0 0x0058 // Nand Flash Timing Parameters 1 973 #define NAND_TIMING_2_CS0 0x005c // Nand Flash Timing Parameters 2 974 #define NAND_ACC_CONTROL_CS1 0x0060 // Nand Flash Access Control 975 #define NAND_CONFIG_CS1 0x0064 // Nand Flash 976 #define NAND_TIMING_1_CS1 0x0068 // Nand Flash Timing Parameters 1 977 #define NAND_TIMING_2_CS1 0x006c // Nand Flash Timing Parameters 2 978 #define NAND_CORR_STAT_THRESHOLD 0x00c0 // Correctable Error Reporting Threshold 979 #define NAND_BLK_WR_PROTECT 0x00c8 // Block Write Protect Enable and Size for EBI_CS0b 980 #define NAND_MULTIPLANE_OPCODES_1 0x00cc // Nand Flash Multiplane Customized Opcodes 981 #define NAND_MULTIPLANE_OPCODES_2 0x00d0 // Nand Flash Multiplane Customized Opcodes 982 #define NAND_MULTIPLANE_CTRL 0x00d4 // Nand Flash Multiplane Control 983 #define NAND_UNCORR_ERROR_COUNT 0x00fc // Read Uncorrectable Event Count 984 #define NAND_CORR_ERROR_COUNT 0x0100 // Read Error Count 985 #define NAND_READ_ERROR_COUNT 0x0104 // Read Error Count 986 #define NAND_BLOCK_LOCK_STATUS 0x0108 // Nand Flash Block Lock Status 987 #define NAND_ECC_CORR_EXT_ADDR 0x010c // ECC Correctable Error Extended Address 988 #define NAND_ECC_CORR_ADDR 0x0110 // ECC Correctable Error Address 989 #define NAND_ECC_UNC_EXT_ADDR 0x0114 // ECC Uncorrectable Error Extended Address 990 #define NAND_ECC_UNC_ADDR 0x0118 // ECC Uncorrectable Error Address 991 #define NAND_FLASH_READ_EXT_ADDR 0x011c // Flash Read Data Extended Address 992 #define NAND_FLASH_READ_ADDR 0x0120 // Flash Read Data Address 993 #define NAND_PROGRAM_PAGE_EXT_ADDR 0x0124 // Page Program Extended Address 994 #define NAND_PROGRAM_PAGE_ADDR 0x0128 // Page Program Address 995 #define NAND_COPY_BACK_EXT_ADDR 0x012c // Copy Back Extended Address 996 #define NAND_COPY_BACK_ADDR 0x0130 // Copy Back Address 997 #define NAND_BLOCK_ERASE_EXT_ADDR 0x0134 // Block Erase Extended Address 998 #define NAND_BLOCK_ERASE_ADDR 0x0138 // Block Erase Address 999 #define NAND_INV_READ_EXT_ADDR 0x013c // Flash Invalid Data Extended Address 1000 #define NAND_INV_READ_ADDR 0x0140 // Flash Invalid Data Address 1001 #define NAND_INIT_STATUS 0x0144 // Initialization status 1002 #define NAND_ONFI_STATUS 0x0148 // ONFI Status 1003 #define NAND_ONFI_DEBUG_DATA 0x014c // ONFI Debug Data 1004 #define NAND_SEMAPHORE 0x0150 // Semaphore 1005 #define NAND_FLASH_DEVICE_ID 0x0194 // Nand Flash Device ID 1006 #define NAND_FLASH_DEVICE_ID_EXT 0x0198 // Nand Flash Extended Device ID 1007 #define NAND_LL_RDDATA 0x019c // Nand Flash Low Level Read Data 1008 1009 #define NAND_SPARE_AREA_READ_OFSn(n) (0x0200+4*(n)) // Nand Flash Spare Area Read Bytes 1010 #define NAND_SPARE_AREA_WRITE_OFSn(n) (0x0280+4*(n)) // Nand Flash Spare Area Write Bytes 8-11 1011 #define NAND_FLASH_CACHEn(n) (0x0400+4*(n)) // Flash Cache Buffer Read Access 1012 1013 #define NAND_DIRECT_READ_RD_MISS 0x0f00 // Interrupt from Nand indicating a read miss on internal memory 1014 #define NAND_BLOCK_ERASE_COMPLETE 0x0f04 // Interrupt from Nand indicating block erase 1015 #define NAND_COPY_BACK_COMPLETE 0x0f08 // Interrupt from Nand indicating Copy-Back complete. 1016 #define NAND_PROGRAM_PAGE_COMPLETE 0x0f0c // Interrupt from nand indicating page program is complete. 1017 #define NAND_RO_CTLR_READY 0x0f10 // Interrupt from nand indicating controller ready 1018 #define NAND_NAND_RB_B 0x0f14 // Interrupt from nand indicating status of Nand Flash ready_bus pin 1019 #define NAND_ECC_MIPS_UNCORR 0x0f18 // Interrupt from Nand indicating Uncorrectable error 1020 #define NAND_ECC_MIPS_CORR 0x0f1c // Interrupt from Nand indicating correctable error 1021 1022 #define NAND_CMD_START_OPCODE __BITS(28,24) 1023 #define NAND_CMD_START_OPCODE_DEFAULT 0 1024 #define NAND_CMD_START_OPCODE_NULL 0 1025 #define NAND_CMD_START_OPCODE_PAGE_READ 1 1026 #define NAND_CMD_START_OPCODE_SPARE_AREA_READ 2 1027 #define NAND_CMD_START_OPCODE_STATUS_READ 3 1028 #define NAND_CMD_START_OPCODE_PROGRAM_PAGE 4 1029 #define NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA 5 1030 #define NAND_CMD_START_OPCODE_COPY_BACK 6 1031 #define NAND_CMD_START_OPCODE_DEVICE_ID_READ 7 1032 #define NAND_CMD_START_OPCODE_BLOCK_ERASE 8 1033 #define NAND_CMD_START_OPCODE_FLASH_RESET 9 1034 #define NAND_CMD_START_OPCODE_BLOCKS_LOCK 10 1035 #define NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN 11 1036 #define NAND_CMD_START_OPCODE_BLOCKS_UNLOCK 12 1037 #define NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS 13 1038 #define NAND_CMD_START_OPCODE_PARAMETER_READ 14 1039 #define NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL 15 1040 #define NAND_CMD_START_OPCODE_LOW_LEVEL_OP 16 1041 #define NAND_CMD_START_OPCODE_PAGE_READ_MULTI 17 1042 #define NAND_CMD_START_OPCODE_STATUS_READ_MULTI 18 1043 #define NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI 19 1044 #define NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI_CACHE 20 1045 #define NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI 21 1046 #define NAND_CMD_START_CSEL __BITS(18,16) 1047 #define NAND_CMD_EXT_ADDRESS __BITS(15,0) 1048 1049 #define BCM_NAND_IDM_IO_CONTROL_APB_LE_MODE_BIT __BIT(24) 1050 1051 1052 #endif /* NAND_PRIVATE */ 1053 1054 #endif /* _ARM_BROADCOM_BCM53XX_REG_H_ */ 1055