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Searched refs:CPU_CONTROL_DC_ENABLE (Results 1 – 19 of 19) sorted by relevance

/netbsd/src/sys/arch/arm/arm/
Dcpufunc.c2641 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2642 { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2643 { "arm9.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2645 { "arm9.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
2658 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE in arm9_setup()
2662 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE in arm9_setup()
2694 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2695 { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2696 { "arm10.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2698 { "arm10.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
[all …]
Darmv6_start.S667 tst r0, #CPU_CONTROL_DC_ENABLE
674 CPU_CONTROL_DC_ENABLE | \
994 ldr r2, =(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
/netbsd/src/sys/arch/evbarm/gemini/
Dgemini_start.S316 CPU_CONTROL_DC_ENABLE | \
323 CPU_CONTROL_DC_ENABLE | \
338 .word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
/netbsd/src/sys/arch/evbarm/armadaxp/
Darmadaxp_start.S73 movw r1, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
120 | CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
/netbsd/src/sys/arch/hpcarm/hpcarm/
Dkloader_pxa2x0.S56 bic r2, r2, #CPU_CONTROL_DC_ENABLE
/netbsd/src/sys/arch/evbarm/stand/board/
Ds3c2410_vector.S73 ldr r0, =(CPU_CONTROL_MMU_ENABLE|CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
Ds3c2800_vector.S105 ldr r0, =(CPU_CONTROL_MMU_ENABLE|CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
/netbsd/src/sys/arch/evbarm/ixm1200/
Dixm1200_start.S65 orr r0, r0, #CPU_CONTROL_DC_ENABLE
/netbsd/src/sys/arch/zaurus/zaurus/
Dkloader_zaurus.S69 bic r2, r2, #CPU_CONTROL_DC_ENABLE
/netbsd/src/sys/arch/evbarm/gumstix/
Dgumstix_start.S106 bic ip, ip, #CPU_CONTROL_DC_ENABLE
/netbsd/src/sys/arch/evbarm/imx23_olinuxino/
Dimx23_olinuxino_start.S132 ldr r1, =(CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE \
/netbsd/src/sys/arch/arm/arm32/
Dlocore.S185 bic r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
Dgenassym.cf161 #define CPU_CONTROL_DC_ENABLE CPU_CONTROL_DC_ENABLE
Dcpu.c739 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) in identify_arm_cpu()
/netbsd/src/sys/arch/evbarm/marvell/
Dmarvell_start.S244 … biceq r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE)
/netbsd/src/sys/arch/acorn32/stand/boot32/
Dstart.S152 … orr r0, r0, #CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_MMU_ENABLE
/netbsd/src/sys/arch/arm/include/
Darmreg.h188 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ macro
216 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
/netbsd/src/sys/arch/epoc32/epoc32/
Depoc32_start.S237 CPU_CONTROL_DC_ENABLE | \
/netbsd/src/sys/arch/evbarm/armadillo/
Darmadillo9_start.S62 bic r2, r2, #CPU_CONTROL_DC_ENABLE