1 /* $NetBSD: cadmusreg.h,v 1.3 2024/07/05 19:28:35 andvar Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _MPC85XX_CADMUSREG_H_ 38 #define _MPC85XX_CADMUSREG_H_ 39 40 #define CM_BASE 0xF8004000 41 42 #define CM_VER 0x00 /* System version register */ 43 #define CM_VER_ID __BITS(4,7) 44 #define CM_VER_ID_GET(n) __SHIFTOUT((n), CM_VER_ID) 45 #define CM_VER_REV __BITS(0,3) 46 #define CM_VER_REV_GET(n) __SHIFTOUT((n), CM_VER_ID) 47 #define CM_CSR 0x01 /* General control/status register */ 48 #define CM_CSR_USER __BITS(6,7) 49 #define CM_CSR_USER_GET(n) __SHIFTOUT((n), CM_CSR_USER) 50 #define CM_CSR_EPHY __BITS(1,3) 51 #define CM_CSR_EPHY_GET(n) __SHIFTOUT((n), CM_CSR_EPHY) 52 #define CM_CSR_LED __BIT(0) 53 #define CM_RST 0x02 /* Reset control register */ 54 #define CM_RST_XRSTEN __BIT(7) /* Enable the NVRAM watchdog timer to function as a general reset input */ 55 #define CM_RST_PHYRST __BIT(6) /* Reset the Ethernet PHY */ 56 #define CM_RST_ATM1RST __BIT(5) /* Reset the FCC1/ATM1 PHYS */ 57 #define CM_RST_ATM2RST __BIT(4) /* Reset the FCC2/ATM2 PHY */ 58 #define CM_RST_MEMRST __BIT(3) /* Reset the memory devices on the daughter card */ 59 #define CM_RST_UTRST __BIT(2) /* Reset the TCOM/ECOM boards */ 60 #define CM_RST_HRESET __BIT(1) /* Assert HRESET */ 61 #define CM_RST_SRESET __BIT(0) /* Assert SRESET */ 62 #define CM_LED 0x05 /* LED data register */ 63 #define CM_PCI 0x06 /* PCI control/status register */ 64 #define CM_PCI_M66O __BIT(7) 65 #define CM_PCI_PCIXCO __BIT(6) 66 #define CM_PCI_M66S __BIT(5) /* PCI V2.3 mode or earlier running at 66MHz */ 67 #define CM_PCI_DUAL __BIT(4) /* Daughter card has selected dual PCI-mode */ 68 #define CM_PCI_PSPEED __BITS(2,3) /* detected PCI speed */ 69 #define CM_PCI_PSPEED_33 __SHIFTIN(0, CM_PCI_PSPEED) 70 #define CM_PCI_PSPEED_66 __SHIFTIN(1, CM_PCI_PSPEED) 71 #define CM_PCI_PCIX __BIT(1) /* the PCI edge connector is connected to a PCI-X backplace */ 72 #define CM_PCI_PCIEN __BIT(0) /* if 1, the PCI backplane is not present */ 73 74 #define CM_DMA 0x07 /* DMA control register */ 75 #define CM_DMA_DMARQ0 __BIT(6) 76 #define CM_DMA_DMACK0 __BIT(5) 77 #define CM_DMA_DMADN0 __BIT(4) 78 #define CM_DMA_DMARQ1 __BIT(2) 79 #define CM_DMA_DMACK1 __BIT(1) 80 #define CM_DMA_DMADN1 __BIT(0) 81 82 #endif /* !_MPC85XX_CADMUSREG_H_ */ 83