1 /* $NetBSD: augpioreg.h,v 1.3 2006/02/18 23:21:06 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _MIPS_ALCHEMY_DEV_AUGPIOREG_H 35 #define _MIPS_ALCHEMY_DEV_AUGPIOREG_H 36 37 #define AUGPIO_NPINS 64 38 39 /* 40 * SYS_GPIO registers -- offset from GPIO_BASE. 41 * 42 * This excludes SYS_PINFUNC, that has to be included in the SYS_BASE 43 * registers -- it is surrounded by other non-GPIO related regs. 44 */ 45 #define AUGPIO_TRIOUTRD 0x00 46 #define AUGPIO_TRIOUTCLR 0x00 47 #define AUGPIO_OUTPUTRD 0x08 48 #define AUGPIO_OUTPUTSET 0x08 49 #define AUGPIO_OUTPUTCLR 0x0C 50 #define AUGPIO_PINSTATERD 0x10 51 #define AUGPIO_PININPUTEN 0x10 52 #define AUGPIO_SIZE 0x14 53 54 /* GPIO2 registers -- offset from GPIO2_BASE */ 55 #define AUGPIO2_DIR 0x00 56 #define AUGPIO2_OUTPUT 0x08 57 #define AUGPIO2_PINSTATE 0x0C 58 #define AUGPIO2_INTEN 0x10 59 #define AUGPIO2_ENABLE 0x14 60 #define AUGPIO2_SIZE 0x18 61 62 #define AUGPIO_GPIO2_ENABLE_CE 0x1 63 #define AUGPIO_GPIO2_ENABLE_MR 0x2 64 65 #endif /* _MIPS_ALCHEMY_DEV_AUPCIREG_H */ 66