1 /* $NetBSD: if_auereg.h,v 1.32 2019/08/23 04:34:51 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/usb/if_auereg.h,v 1.2 2000/01/08 06:52:36 wpaul Exp $ 35 */ 36 37 /* 38 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet 39 * chip. The Pegasus uses a total of four USB endpoints: the control 40 * endpoint (0), a bulk read endpoint for receiving packets (1), 41 * a bulk write endpoint for sending packets (2) and an interrupt 42 * endpoint for passing RX and TX status (3). Endpoint 0 is used 43 * to read and write the ethernet module's registers. All registers 44 * are 8 bits wide. 45 * 46 * Packet transfer is done in 64 byte chunks. The last chunk in a 47 * transfer is denoted by having a length less that 64 bytes. For 48 * the RX case, the data includes an optional RX status word. 49 */ 50 51 #include <sys/rndsource.h> 52 53 #define AUE_UR_READREG 0xF0 54 #define AUE_UR_WRITEREG 0xF1 55 56 #define AUE_CONFIG_NO 1 57 #define AUE_IFACE_IDX 0 58 59 /* 60 * Note that while the ADMtek technically has four 61 * endpoints, the control endpoint (endpoint 0) is 62 * regarded as special by the USB code and drivers 63 * don't have direct access to it. (We access it 64 * using usbd_do_request() when reading/writing 65 * registers.) Consequently, our endpoint indexes 66 * don't match those in the ADMtek Pegasus manual: 67 * we consider the RX data endpoint to be index 0 68 * and work up from there. 69 */ 70 71 #define AUE_CTL0 0x00 72 #define AUE_CTL1 0x01 73 #define AUE_CTL2 0x02 74 #define AUE_MAR0 0x08 75 #define AUE_MAR1 0x09 76 #define AUE_MAR2 0x0A 77 #define AUE_MAR3 0x0B 78 #define AUE_MAR4 0x0C 79 #define AUE_MAR5 0x0D 80 #define AUE_MAR6 0x0E 81 #define AUE_MAR7 0x0F 82 #define AUE_MAR AUE_MAR0 83 #define AUE_PAR0 0x10 84 #define AUE_PAR1 0x11 85 #define AUE_PAR2 0x12 86 #define AUE_PAR3 0x13 87 #define AUE_PAR4 0x14 88 #define AUE_PAR5 0x15 89 #define AUE_PAR AUE_PAR0 90 #define AUE_PAUSE0 0x18 91 #define AUE_PAUSE1 0x19 92 #define AUE_PAUSE AUE_PAUSE0 93 #define AUE_RX_FLOWCTL_CNT 0x1A 94 #define AUE_RX_FLOWCTL_FIFO 0x1B 95 #define AUE_REG_1D 0x1D 96 #define AUE_EE_REG 0x20 97 #define AUE_EE_DATA0 0x21 98 #define AUE_EE_DATA1 0x22 99 #define AUE_EE_DATA AUE_EE_DATA0 100 #define AUE_EE_CTL 0x23 101 #define AUE_PHY_ADDR 0x25 102 #define AUE_PHY_DATA0 0x26 103 #define AUE_PHY_DATA1 0x27 104 #define AUE_PHY_DATA AUE_PHY_DATA0 105 #define AUE_PHY_CTL 0x28 106 #define AUE_USB_STS 0x2A 107 #define AUE_TXSTAT0 0x2B 108 #define AUE_TXSTAT1 0x2C 109 #define AUE_TXSTAT AUE_TXSTAT0 110 #define AUE_RXSTAT 0x2D 111 #define AUE_PKTLOST0 0x2E 112 #define AUE_PKTLOST1 0x2F 113 #define AUE_PKTLOST AUE_PKTLOST0 114 115 #define AUE_REG_7B 0x7B 116 #define AUE_GPIO0 0x7E 117 #define AUE_GPIO1 0x7F 118 #define AUE_REG_81 0x81 119 120 #define AUE_CTL0_INCLUDE_RXCRC 0x01 121 #define AUE_CTL0_ALLMULTI 0x02 122 #define AUE_CTL0_STOP_BACKOFF 0x04 123 #define AUE_CTL0_RXSTAT_APPEND 0x08 124 #define AUE_CTL0_WAKEON_ENB 0x10 125 #define AUE_CTL0_RXPAUSE_ENB 0x20 126 #define AUE_CTL0_RX_ENB 0x40 127 #define AUE_CTL0_TX_ENB 0x80 128 129 #define AUE_CTL1_HOMELAN 0x04 130 #define AUE_CTL1_RESETMAC 0x08 131 #define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */ 132 #define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */ 133 #define AUE_CTL1_DELAYHOME 0x40 134 135 #define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */ 136 #define AUE_CTL2_RX_BADFRAMES 0x02 137 #define AUE_CTL2_RX_PROMISC 0x04 138 #define AUE_CTL2_LOOPBACK 0x08 139 #define AUE_CTL2_EEPROMWR_ENB 0x10 140 #define AUE_CTL2_EEPROM_LOAD 0x20 141 142 #define AUE_EECTL_WRITE 0x01 143 #define AUE_EECTL_READ 0x02 144 #define AUE_EECTL_DONE 0x04 145 146 #define AUE_PHYCTL_PHYREG 0x1F 147 #define AUE_PHYCTL_WRITE 0x20 148 #define AUE_PHYCTL_READ 0x40 149 #define AUE_PHYCTL_DONE 0x80 150 151 #define AUE_USBSTS_SUSPEND 0x01 152 #define AUE_USBSTS_RESUME 0x02 153 154 #define AUE_TXSTAT0_JABTIMO 0x04 155 #define AUE_TXSTAT0_CARLOSS 0x08 156 #define AUE_TXSTAT0_NOCARRIER 0x10 157 #define AUE_TXSTAT0_LATECOLL 0x20 158 #define AUE_TXSTAT0_EXCESSCOLL 0x40 159 #define AUE_TXSTAT0_UNDERRUN 0x80 160 161 #define AUE_TXSTAT1_PKTCNT 0x0F 162 #define AUE_TXSTAT1_FIFO_EMPTY 0x40 163 #define AUE_TXSTAT1_FIFO_FULL 0x80 164 165 #define AUE_RXSTAT_OVERRUN 0x01 166 #define AUE_RXSTAT_PAUSE 0x02 167 168 #define AUE_GPIO_IN0 0x01 169 #define AUE_GPIO_OUT0 0x02 170 #define AUE_GPIO_SEL0 0x04 171 #define AUE_GPIO_IN1 0x08 172 #define AUE_GPIO_OUT1 0x10 173 #define AUE_GPIO_SEL1 0x20 174 175 struct aue_intrpkt { 176 uint8_t aue_txstat0; 177 uint8_t aue_txstat1; 178 uint8_t aue_rxstat; 179 uint8_t aue_rxlostpkt0; 180 uint8_t aue_rxlostpkt1; 181 uint8_t aue_wakeupstat; 182 uint8_t aue_rsvd; 183 uint8_t _pad; 184 }; 185 #define AUE_INTR_PKTLEN 8 186 187 struct aue_rxpkt { 188 uWord aue_pktlen; 189 uByte aue_rxstat; 190 }; 191 192 #define AUE_RXSTAT_MCAST 0x01 193 #define AUE_RXSTAT_GIANT 0x02 194 #define AUE_RXSTAT_RUNT 0x04 195 #define AUE_RXSTAT_CRCERR 0x08 196 #define AUE_RXSTAT_DRIBBLE 0x10 197 #define AUE_RXSTAT_MASK 0x1E 198