1 /* $Id: imx23_apbdmavar.h,v 1.2 2015/01/10 12:13:00 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_IMX_IMX23_APBDMAVAR_H_ 33 #define _ARM_IMX_IMX23_APBDMAVAR_H_ 34 35 #include <sys/cdefs.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/mutex.h> 40 41 /* DMA command control register bits. */ 42 #define APBDMA_CMD_XFER_COUNT __BITS(31, 16) 43 #define APBDMA_CMD_CMDPIOWORDS __BITS(15, 12) 44 #define APBDMA_CMD_RESERVED __BITS(11, 9) 45 #define APBDMA_CMD_HALTONTERMINATE __BIT(8) 46 #define APBDMA_CMD_WAIT4ENDCMD __BIT(7) 47 #define APBDMA_CMD_SEMAPHORE __BIT(6) 48 #define APBDMA_CMD_NANDWAIT4READY __BIT(5) 49 #define APBDMA_CMD_NANDLOCK __BIT(4) 50 #define APBDMA_CMD_IRQONCMPLT __BIT(3) 51 #define APBDMA_CMD_CHAIN __BIT(2) 52 #define APBDMA_CMD_COMMAND __BITS(1, 0) 53 54 /* DMA command types. */ 55 #define APBDMA_CMD_NO_DMA_XFER 0 56 #define APBDMA_CMD_DMA_WRITE 1 57 #define APBDMA_CMD_DMA_READ 2 58 #define APBDMA_CMD_DMA_SENSE 3 59 60 /* Flags. */ 61 #define F_APBH_DMA __BIT(0) 62 #define F_APBX_DMA __BIT(1) 63 64 /* Number of channels. */ 65 #define AHBH_DMA_CHANNELS 8 66 #define AHBX_DMA_CHANNELS 16 67 68 /* APBH DMA channel assignments. */ 69 #define APBH_DMA_CHANNEL_RES0 0 /* Reserved. */ 70 #define APBH_DMA_CHANNEL_SSP1 1 /* SSP1. */ 71 #define APBH_DMA_CHANNEL_SSP2 2 /* SSP2. */ 72 #define APBH_DMA_CHANNEL_RES1 3 /* Reserved. */ 73 #define APBH_DMA_CHANNEL_NAND_DEVICE0 4 /* NAND_DEVICE0. */ 74 #define APBH_DMA_CHANNEL_NAND_DEVICE1 5 /* NAND_DEVICE1. */ 75 #define APBH_DMA_CHANNEL_NAND_DEVICE2 6 /* NAND_DEVICE2. */ 76 #define APBH_DMA_CHANNEL_NAND_DEVICE3 7 /* NAND_DEVICE3. */ 77 78 /* APBX DMA channel assignments. */ 79 #define APBX_DMA_CHANNEL_AUDIO_ADC 0 /* Audio ADCs. */ 80 #define APBX_DMA_CHANNEL_AUDIO_DAC 1 /* Audio DACs. */ 81 #define APBX_DMA_CHANNEL_SPDIF_TX 2 /* SPDIF TX. */ 82 #define APBX_DMA_CHANNEL_I2C 3 /* I2C. */ 83 #define APBX_DMA_CHANNEL_SAIF1 4 /* SAIF1. */ 84 #define APBX_DMA_CHANNEL_RES0 5 /* Reserved. */ 85 #define APBX_DMA_CHANNEL_UART1_RX 6 /* UART1 RX, IrDA RX. */ 86 #define APBX_DMA_CHANNEL_UART1_TX 7 /* UART1 TX, IrDA TX. */ 87 #define APBX_DMA_CHANNEL_UART2_RX 8 /* UART2 RX. */ 88 #define APBX_DMA_CHANNEL_UART2_TX 9 /* UART2 TX. */ 89 #define APBX_DMA_CHANNEL_SAIF2 10 /* SAIF2. */ 90 #define APBX_DMA_CHANNEL_RES1 11 /* Reserved. */ 91 #define APBX_DMA_CHANNEL_RES2 12 /* Reserved. */ 92 #define APBX_DMA_CHANNEL_RES3 13 /* Reserved. */ 93 #define APBX_DMA_CHANNEL_RES4 14 /* Reserved. */ 94 #define APBX_DMA_CHANNEL_RES5 15 /* Reserved. */ 95 96 /* Return codes for apbdma_intr_status() */ 97 #define DMA_IRQ_CMDCMPLT 0 98 #define DMA_IRQ_TERM 1 99 #define DMA_IRQ_BUS_ERROR 2 100 101 #define PIO_WORDS_MAX 15 102 103 /* 104 * How many PIO words apbdma_command structure has. 105 * 106 * XXX: If you change this value, make sure drivers are prepared for that. 107 * That means you have to allocate enough DMA memory for command chains. 108 */ 109 #define PIO_WORDS 3 110 111 typedef struct apbdma_softc { 112 device_t sc_dev; 113 bus_dma_tag_t sc_dmat; 114 bus_space_handle_t sc_ioh; 115 bus_space_tag_t sc_iot; 116 kmutex_t sc_lock; 117 u_int flags; 118 } *apbdma_softc_t; 119 120 typedef struct apbdma_command { 121 void *next; /* Physical address. */ 122 uint32_t control; 123 void *buffer; /* Physical address. */ 124 uint32_t pio_words[PIO_WORDS]; 125 } *apbdma_command_t; 126 127 void apbdma_cmd_chain(apbdma_command_t, apbdma_command_t, void *, bus_dmamap_t); 128 void apbdma_cmd_buf(apbdma_command_t, bus_addr_t, bus_dmamap_t); 129 void apbdma_chan_init(struct apbdma_softc *, unsigned int); 130 void apbdma_chan_set_chain(struct apbdma_softc *, unsigned int, bus_dmamap_t); 131 void apbdma_run(struct apbdma_softc *, unsigned int); 132 void apbdma_ack_intr(struct apbdma_softc *, unsigned int); 133 void apbdma_ack_error_intr(struct apbdma_softc *, unsigned int); 134 unsigned int apbdma_intr_status(struct apbdma_softc *, unsigned int); 135 void apbdma_chan_reset(struct apbdma_softc *, unsigned int); 136 void apbdma_wait(struct apbdma_softc *, unsigned int); 137 138 #endif /* !_ARM_IMX_IMX23_APBDMAVAR_H_ */ 139