1 /* $MirOS: src/sys/dev/ic/isacsx.h,v 1.2 2013/10/31 20:06:53 tg Exp $ */ 2 /* ISDN4BSD code */ 3 /* $NetBSD: isacsx.h,v 1.1 2002/10/25 21:03:48 leo Exp $ */ 4 /* 5 * Copyright © 2013 6 * Thorsten “mirabilos” Glaser <tg@mirbsd.org> 7 * Copyright (c) 2001 Gary Jennejohn. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 4. Altered versions must be plainly marked as such, and must not be 22 * misrepresented as being the original software and/or documentation. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 *--------------------------------------------------------------------------- 37 * 38 * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h,v 1.1.2.1 2002/04/25 20:26:50 gj Exp $ 39 * 40 * last edit-date: [Wed Jan 24 09:10:42 2001] 41 * 42 *---------------------------------------------------------------------------*/ 43 44 #ifndef I4B_ISACSX_H_ 45 #define I4B_ISACSX_H_ 46 47 /* 48 * XXX: Leo: It is unclear to me if this is a necessity for the isacsx too... 49 * 50 * The ISAC databook specifies a delay of 2.5 DCL clock cycles between 51 * writes to the ISAC command register CMDR. This is the delay used to 52 * satisfy this requirement. 53 */ 54 #define I4B_ISAC_CMDRWRDELAY 30 55 56 #if (I4B_ISAC_CMDRWRDELAY > 0) 57 #define ISACCMDRWRDELAY() DELAY(I4B_ISAC_CMDRWRDELAY) 58 #else 59 #warning "I4B_ISAC_CMDRWRDELAY set to 0!" 60 #define ISACCMDRWRDELAY() 61 #endif 62 63 #define ISACSX_FIFO_LEN 32 /* 32 bytes FIFO on chip */ 64 65 #define ISACSX_V13 0x01 66 67 /* 68 * definitions of registers and bits for the ISAC-SX ISDN chip. 69 */ 70 71 typedef struct isacsx_reg { 72 73 /* 32 byte deep FIFO always first */ 74 75 unsigned char isacsx_fifo [ISACSX_FIFO_LEN]; 76 77 /* most registers can be read/written, but have different names */ 78 /* so define a union with read/write names to make that clear */ 79 80 union { 81 struct { 82 unsigned char isacsx_istad; 83 unsigned char isacsx_stard; 84 unsigned char isacsx_moded; 85 unsigned char isacsx_exmd1; 86 unsigned char isacsx_timr1; 87 unsigned char dummy_25; 88 unsigned char isacsx_rbcld; 89 unsigned char isacsx_rbchd; 90 unsigned char isacsx_rstad; 91 unsigned char isacsx_tmd; 92 unsigned char dummy_2a; 93 unsigned char dummy_2b; 94 unsigned char dummy_2c; 95 unsigned char dummy_2d; 96 unsigned char isacsx_cir0; 97 unsigned char isacsx_codr1; 98 unsigned char isacsx_tr_conf0; 99 unsigned char isacsx_tr_conf1; 100 unsigned char isacsx_tr_conf2; 101 unsigned char isacsx_tr_sta; 102 unsigned char dummy_34; 103 unsigned char isacsx_sqrr1; 104 unsigned char isacsx_sqrr2; 105 unsigned char isacsx_sqrr3; 106 unsigned char isacsx_istatr; 107 unsigned char isacsx_masktr; 108 unsigned char dummy_3a; 109 unsigned char dummy_3b; 110 unsigned char isacsx_acgf2; 111 unsigned char dummy_3d; 112 unsigned char dummy_3e; 113 unsigned char dummy_3f; 114 unsigned char isacsx_cda10; 115 unsigned char isacsx_cda11; 116 unsigned char isacsx_cda20; 117 unsigned char isacsx_cda21; 118 unsigned char isacsx_cda_tsdp10; 119 unsigned char isacsx_cda_tsdp11; 120 unsigned char isacsx_cda_tsdp20; 121 unsigned char isacsx_cda_tsdp21; 122 unsigned char dummy_48; 123 unsigned char dummy_49; 124 unsigned char dummy_4a; 125 unsigned char dummy_4b; 126 unsigned char isacsx_tr_tsdp_bc1; 127 unsigned char isacsx_tr_tsdp_bc2; 128 unsigned char isacsx_cda1_cr; 129 unsigned char isacsx_cda2_cr; 130 unsigned char isacsx_tr_cr; 131 unsigned char dummy_51; 132 unsigned char dummy_52; 133 unsigned char isacsx_dci_cr; 134 unsigned char isacsx_mon_cr; 135 unsigned char isacsx_sds_cr; 136 unsigned char dummy_56; 137 unsigned char isacsx_iom_cr; 138 unsigned char isacsx_sti; 139 unsigned char isacsx_msti; 140 unsigned char isacsx_sds_conf; 141 unsigned char isacsx_mcda; 142 unsigned char isacsx_mor; 143 unsigned char isacsx_mosr; 144 unsigned char isacsx_mocr; 145 unsigned char isacsx_msta; 146 unsigned char isacsx_ista; 147 unsigned char isacsx_auxi; 148 unsigned char isacsx_mode1; 149 unsigned char isacsx_mode2; 150 unsigned char isacsx_id; 151 unsigned char isacsx_timr2; 152 unsigned char dummy_66; 153 unsigned char dummy_67; 154 unsigned char dummy_68; 155 unsigned char dummy_69; 156 unsigned char dummy_6a; 157 unsigned char dummy_6b; 158 unsigned char dummy_6c; 159 unsigned char dummy_6d; 160 unsigned char dummy_6e; 161 unsigned char dummy_6f; 162 } isacsx_r; 163 struct { 164 unsigned char isacsx_maskd; 165 unsigned char isacsx_cmdrd; 166 unsigned char isacsx_moded; 167 unsigned char isacsx_exmd1; 168 unsigned char isacsx_timr1; 169 unsigned char isacsx_sap1; 170 unsigned char isacsx_sap2; 171 unsigned char isacsx_tei1; 172 unsigned char isacsx_tei2; 173 unsigned char isacsx_tmd; 174 unsigned char dummy_2a; 175 unsigned char dummy_2b; 176 unsigned char dummy_2c; 177 unsigned char dummy_2d; 178 unsigned char isacsx_cix0; 179 unsigned char isacsx_codx1; 180 unsigned char isacsx_tr_conf0; 181 unsigned char isacsx_tr_conf1; 182 unsigned char isacsx_tr_conf2; 183 unsigned char dummy_33; 184 unsigned char dummy_34; 185 unsigned char isacsx_sqrx1; 186 unsigned char dummy_36; 187 unsigned char dummy_37; 188 unsigned char dummy_38; 189 unsigned char isacsx_masktr; 190 unsigned char dummy_3a; 191 unsigned char dummy_3b; 192 unsigned char isacsx_acgf2; 193 unsigned char dummy_3d; 194 unsigned char dummy_3e; 195 unsigned char dummy_3f; 196 unsigned char isacsx_cda10; 197 unsigned char isacsx_cda11; 198 unsigned char isacsx_cda20; 199 unsigned char isacsx_cda21; 200 unsigned char isacsx_cda_tsdp10; 201 unsigned char isacsx_cda_tsdp11; 202 unsigned char isacsx_cda_tsdp20; 203 unsigned char isacsx_cda_tsdp21; 204 unsigned char dummy_48; 205 unsigned char dummy_49; 206 unsigned char dummy_4a; 207 unsigned char dummy_4b; 208 unsigned char isacsx_tr_tsdp_bc1; 209 unsigned char isacsx_tr_tsdp_bc2; 210 unsigned char isacsx_cda1_cr; 211 unsigned char isacsx_cda2_cr; 212 unsigned char isacsx_tr_cr; 213 unsigned char dummy_51; 214 unsigned char dummy_52; 215 unsigned char isacsx_dci_cr; 216 unsigned char isacsx_mon_cr; 217 unsigned char isacsx_sds_cr; 218 unsigned char dummy_56; 219 unsigned char isacsx_iom_cr; 220 unsigned char isacsx_asti; 221 unsigned char isacsx_msti; 222 unsigned char isacsx_sds_conf; 223 unsigned char dummy_5b; 224 unsigned char isacsx_mox; 225 unsigned char dummy_5d; 226 unsigned char isacsx_mocr; 227 unsigned char isacsx_mconf; 228 unsigned char isacsx_mask; 229 unsigned char isacsx_auxm; 230 unsigned char isacsx_mode1; 231 unsigned char isacsx_mode2; 232 unsigned char isacsx_sres; 233 unsigned char isacsx_timr2; 234 unsigned char dummy_66; 235 unsigned char dummy_67; 236 unsigned char dummy_68; 237 unsigned char dummy_69; 238 unsigned char dummy_6a; 239 unsigned char dummy_6b; 240 unsigned char dummy_6c; 241 unsigned char dummy_6d; 242 unsigned char dummy_6e; 243 unsigned char dummy_6f; 244 } isacsx_w; 245 } isacsx_rw; 246 } __attribute__((__packed__)) isacsx_reg_t; 247 248 #define REG_OFFSET(type, field) (int)(&(((type *)0)->field)) 249 250 /* ISACSX read registers */ 251 252 #define i_istad isacsx_rw.isacsx_r.isacsx_istad 253 #define I_ISTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istad) 254 #define i_stard isacsx_rw.isacsx_r.isacsx_stard 255 #define I_STARD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_stard) 256 #define i_rmoded isacsx_rw.isacsx_r.isacsx_moded 257 #define I_RMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_moded) 258 #define i_rexmd1 isacsx_rw.isacsx_r.isacsx_exmd1 259 #define I_REXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_exmd1) 260 #define i_rtimr1 isacsx_rw.isacsx_r.isacsx_timr1 261 #define I_RTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr1) 262 #define i_rbcld isacsx_rw.isacsx_r.isacsx_rbcld 263 #define I_RBCLD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbcld) 264 #define i_rbchd isacsx_rw.isacsx_r.isacsx_rbchd 265 #define I_RBCHD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbchd) 266 #define i_rstad isacsx_rw.isacsx_r.isacsx_rstad 267 #define I_RSTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rstad) 268 #define i_rtmd isacsx_rw.isacsx_r.isacsx_tmd 269 #define I_RTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tmd) 270 #define i_cir0 isacsx_rw.isacsx_r.isacsx_cir0 271 #define I_CIR0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cir0) 272 #define i_codr1 isacsx_rw.isacsx_r.isacsx_codr1 273 #define I_CODR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_codr1) 274 #define i_rtr_conf0 isacsx_rw.isacsx_r.isacsx_tr_conf0 275 #define I_RTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf0) 276 #define i_rtr_conf1 isacsx_rw.isacsx_r.isacsx_tr_conf1 277 #define I_RTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf1) 278 #define i_rtr_conf2 isacsx_rw.isacsx_r.isacsx_tr_conf2 279 #define I_RTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf2) 280 #define i_sta isacsx_rw.isacsx_r.isacsx_sta 281 #define I_STA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sta) 282 #define i_sqrr1 isacsx_rw.isacsx_r.isacsx_sqrr1 283 #define I_SQRR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr1) 284 #define i_sqrr2 isacsx_rw.isacsx_r.isacsx_sqrr2 285 #define I_SQRR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr2) 286 #define i_sqrr3 isacsx_rw.isacsx_r.isacsx_sqrr3 287 #define I_SQRR3 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr3) 288 #define i_istatr isacsx_rw.isacsx_r.isacsx_istatr 289 #define I_ISTATR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istatr) 290 #define i_rmasktr isacsx_rw.isacsx_r.isacsx_masktr 291 #define I_RMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_masktr) 292 #define i_racgf2 isacsx_rw.isacsx_r.isacsx_acgf2 293 #define I_RACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_acgf2) 294 #define i_rcda10 isacsx_rw.isacsx_r.isacsx_cda10 295 #define I_RCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda10) 296 #define i_rcda11 isacsx_rw.isacsx_r.isacsx_cda11 297 #define I_RCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11) 298 #define i_rcda20 isacsx_rw.isacsx_r.isacsx_cda20 299 #define I_RCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20) 300 #define i_rcda21 isacsx_rw.isacsx_r.isacsx_cda21 301 #define I_RCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21) 302 #define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10 303 #define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10) 304 #define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11 305 #define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11) 306 #define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20 307 #define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20) 308 #define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21 309 #define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21) 310 #define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1 311 #define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1) 312 #define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2 313 #define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2) 314 #define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr 315 #define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr) 316 #define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr 317 #define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr) 318 #define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr 319 #define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr) 320 #define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr 321 #define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr) 322 #define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr 323 #define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr) 324 #define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr 325 #define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr) 326 #define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr 327 #define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr) 328 #define i_sti isacsx_rw.isacsx_r.isacsx_sti 329 #define I_STI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sti) 330 #define i_msti isacsx_rw.isacsx_r.isacsx_msti 331 #define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti) 332 #define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf 333 #define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf) 334 #define i_mcda isacsx_rw.isacsx_r.isacsx_mcda 335 #define I_MCDA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mcda) 336 #define i_mor isacsx_rw.isacsx_r.isacsx_mor 337 #define I_MOR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mor) 338 #define i_mosr isacsx_rw.isacsx_r.isacsx_mosr 339 #define I_MOSR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mosr) 340 #define i_rmocr isacsx_rw.isacsx_r.isacsx_mocr 341 #define I_RMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mocr) 342 #define i_msta isacsx_rw.isacsx_r.isacsx_msta 343 #define I_MSTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msta) 344 #define i_ista isacsx_rw.isacsx_r.isacsx_ista 345 #define I_ISTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_ista) 346 #define i_auxi isacsx_rw.isacsx_r.isacsx_auxi 347 #define I_AUXI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_auxi) 348 #define i_rmode1 isacsx_rw.isacsx_r.isacsx_mode1 349 #define I_RMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode1) 350 #define i_rmode2 isacsx_rw.isacsx_r.isacsx_mode2 351 #define I_RMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode2) 352 #define i_id isacsx_rw.isacsx_r.isacsx_id 353 #define I_ID REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_id) 354 #define i_rtimr2 isacsx_rw.isacsx_r.isacsx_timr2 355 #define I_RTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr2) 356 357 /* ISAC write registers - isacsx_mode, isacsx_timr, isacsx_star2, isacsx_spcr, */ 358 /* isacsx_c1r, isacsx_c2r, isacsx_adf2 see read registers */ 359 360 #define i_maskd isacsx_rw.isacsx_w.isacsx_maskd 361 #define I_MASKD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_maskd) 362 #define i_cmdrd isacsx_rw.isacsx_w.isacsx_cmdrd 363 #define I_CMDRD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cmdrd) 364 #define i_wmoded isacsx_rw.isacsx_w.isacsx_moded 365 #define I_WMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_moded) 366 #define i_wexmd1 isacsx_rw.isacsx_w.isacsx_exmd1 367 #define I_WEXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_exmd1) 368 #define i_wtimr1 isacsx_rw.isacsx_w.isacsx_timr1 369 #define I_WTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr1) 370 #define i_sap1 isacsx_rw.isacsx_w.isacsx_sap1 371 #define I_SAP1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap1) 372 #define i_sap2 isacsx_rw.isacsx_w.isacsx_sap2 373 #define I_SAP2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap2) 374 #define i_tei1 isacsx_rw.isacsx_w.isacsx_tei1 375 #define i_tei2 isacsx_rw.isacsx_w.isacsx_tei2 376 #define i_wtmd isacsx_rw.isacsx_w.isacsx_tmd 377 #define I_WTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tmd) 378 #define i_cix0 isacsx_rw.isacsx_w.isacsx_cix0 379 #define I_CIX0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cix0) 380 #define i_codx1 isacsx_rw.isacsx_w.isacsx_codx1 381 #define I_CODX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_codx1) 382 #define i_wtr_conf0 isacsx_rw.isacsx_w.isacsx_tr_conf0 383 #define I_WTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf0) 384 #define i_wtr_conf1 isacsx_rw.isacsx_w.isacsx_tr_conf1 385 #define I_WTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf1) 386 #define i_wtr_conf2 isacsx_rw.isacsx_w.isacsx_tr_conf2 387 #define I_WTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf2) 388 #define i_sqrx1 isacsx_rw.isacsx_w.isacsx_sqrx1 389 #define I_SQRX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sqrx1) 390 #define i_wmasktr isacsx_rw.isacsx_w.isacsx_masktr 391 #define I_WMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_masktr) 392 #define i_wacgf2 isacsx_rw.isacsx_w.isacsx_acgf2 393 #define I_WACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_acgf2) 394 #define i_wcda10 isacsx_rw.isacsx_w.isacsx_cda10 395 #define I_WCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cda10) 396 #define i_wcda11 isacsx_rw.isacsx_r.isacsx_cda11 397 #define I_WCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11) 398 #define i_wcda20 isacsx_rw.isacsx_r.isacsx_cda20 399 #define I_WCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20) 400 #define i_wcda21 isacsx_rw.isacsx_r.isacsx_cda21 401 #define I_WCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21) 402 #define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10 403 #define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10) 404 #define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11 405 #define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11) 406 #define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20 407 #define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20) 408 #define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21 409 #define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21) 410 #define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1 411 #define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1) 412 #define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2 413 #define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2) 414 #define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr 415 #define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr) 416 #define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr 417 #define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr) 418 #define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr 419 #define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr) 420 #define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr 421 #define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr) 422 #define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr 423 #define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr) 424 #define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr 425 #define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr) 426 #define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr 427 #define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr) 428 #define i_asti isacsx_rw.isacsx_r.isacsx_asti 429 #define I_ASTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_asti) 430 #define i_msti isacsx_rw.isacsx_r.isacsx_msti 431 #define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti) 432 #define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf 433 #define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf) 434 #define i_mox isacsx_rw.isacsx_w.isacsx_mox 435 #define I_MOX REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mox) 436 #define i_wmocr isacsx_rw.isacsx_w.isacsx_mocr 437 #define I_WMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mocr) 438 #define i_mconf isacsx_rw.isacsx_w.isacsx_mconf 439 #define I_MCONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mconf) 440 #define i_mask isacsx_rw.isacsx_w.isacsx_mask 441 #define I_MASK REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mask) 442 #define i_auxm isacsx_rw.isacsx_w.isacsx_auxm 443 #define I_AUXM REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_auxm) 444 #define i_wmode1 isacsx_rw.isacsx_w.isacsx_mode1 445 #define I_WMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode1) 446 #define i_wmode2 isacsx_rw.isacsx_w.isacsx_mode2 447 #define I_WMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode2) 448 #define i_sres isacsx_rw.isacsx_w.isacsx_sres 449 #define I_SRES REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sres) 450 #define i_wtimr2 isacsx_rw.isacsx_w.isacsx_timr2 451 #define I_WTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr2) 452 453 #define ISACSX_ISTAD_RME 0x80 454 #define ISACSX_ISTAD_RPF 0x40 455 #define ISACSX_ISTAD_RFO 0x20 456 #define ISACSX_ISTAD_XPR 0x10 457 #define ISACSX_ISTAD_XMR 0x08 458 #define ISACSX_ISTAD_XDU 0x04 459 460 #define ISACSX_MASKD_RME 0x80 461 #define ISACSX_MASKD_RPF 0x40 462 #define ISACSX_MASKD_RFO 0x20 463 #define ISACSX_MASKD_XPR 0x10 464 #define ISACSX_MASKD_XMR 0x08 465 #define ISACSX_MASKD_XDU 0x04 466 /* these must always be set */ 467 #define ISACSX_MASKD_LOW 0x03 468 #define ISACSX_MASKD_ALL 0xff 469 470 #define ISACSX_STARD_XDOV 0x80 471 #define ISACSX_STARD_XFW 0x40 472 #define ISACSX_STARD_RAC1 0x08 473 #define ISACSX_STARD_XAC1 0x02 474 475 #define ISACSX_CMDRD_RMC 0x80 476 #define ISACSX_CMDRD_RRES 0x40 477 #define ISACSX_CMDRD_STI 0x10 478 #define ISACSX_CMDRD_XTF 0x08 479 #define ISACSX_CMDRD_XME 0x02 480 #define ISACSX_CMDRD_XRES 0x01 481 482 #define ISACSX_MODED_MDS2 0x80 483 #define ISACSX_MODED_MDS1 0x40 484 #define ISACSX_MODED_MDS0 0x20 485 #define ISACSX_MODED_RAC 0x08 486 #define ISACSX_MODED_DIM2 0x04 487 #define ISACSX_MODED_DIM1 0x02 488 #define ISACSX_MODED_DIM0 0x01 489 490 /* default */ 491 #define ISACSX_EXMD1_XFBS_32 0x00 /* XFIFO is 32 bytes */ 492 #define ISACSX_EXMD1_XFBS_16 0x80 /* XFIFO is 16 bytes */ 493 /* default */ 494 #define ISACSX_EXMD1_RFBS_32 0x00 /* XFIFO is 32 bytes */ 495 #define ISACSX_EXMD1_RFBS_16 0x20 /* XFIFO is 16 bytes */ 496 #define ISACSX_EXMD1_RFBS_08 0x40 /* XFIFO is 8 bytes */ 497 #define ISACSX_EXMD1_RFBS_04 0x60 /* XFIFO is 4 bytes */ 498 #define ISACSX_EXMD1_SRA 0x10 499 #define ISACSX_EXMD1_XCRC 0x08 500 #define ISACSX_EXMD1_RCRC 0x04 501 #define ISACSX_EXMD1_ITF 0x01 502 503 #define ISACSX_RSTAD_VFR 0x80 504 #define ISACSX_RSTAD_RDO 0x40 505 #define ISACSX_RSTAD_CRC 0x20 506 #define ISACSX_RSTAD_RAB 0x10 507 #define ISACSX_RSTAD_SA1 0x08 508 #define ISACSX_RSTAD_SA0 0x04 509 #define ISACSX_RSTAD_CR 0x02 510 #define ISACSX_RSTAD_TA 0x01 511 512 #define ISACSX_RSTAD_MASK 0xf0 /* the interesting bits */ 513 514 #define ISACSX_RBCHD_OV 0x10 515 /* the other 4 bits are the high bits of the receive byte count */ 516 517 #define ISACSX_CIR0_CIC0 0x08 518 /* CODR0 >> 4 */ 519 #define ISACSX_CIR0_IPU 0x07 520 #define ISACSX_CIR0_IDR 0x00 521 #define ISACSX_CIR0_ISD 0x02 522 #define ISACSX_CIR0_IDIS 0x03 523 #define ISACSX_CIR0_IEI 0x06 524 #define ISACSX_CIR0_IRSY 0x04 525 #define ISACSX_CIR0_IARD 0x08 526 #define ISACSX_CIR0_ITI 0x0a 527 #define ISACSX_CIR0_IATI 0x0b 528 #define ISACSX_CIR0_IAI8 0x0c 529 #define ISACSX_CIR0_IAI10 0x0d 530 #define ISACSX_CIR0_IDID 0x0f 531 532 #define ISACSX_IOM_CR_SPU 0x80 533 #define ISACSX_IOM_CR_CI_CS 0x20 534 #define ISACSX_IOM_CR_TIC_DIS 0x10 535 #define ISACSX_IOM_CR_EN_BCL 0x08 536 #define ISACSX_IOM_CR_CLKM 0x04 537 #define ISACSX_IOM_CR_DIS_OD 0x02 538 #define ISACSX_IOM_CR_DIS_IOM 0x01 539 540 #define ISACSX_CI_MASK 0x0f 541 542 #define ISACSX_CIX0_BAC 0x01 543 /* in IOM-2 mode the low bits are always 1 */ 544 #define ISACSX_CIX0_LOW 0x0e 545 /* C/I codes from bits 7-4 (>> 4 & 0xf) */ 546 /* the commands */ 547 #define ISACSX_CIX0_CTIM 0 548 #define ISACSX_CIX0_CRS 0x01 549 /* test mode only */ 550 #define ISACSX_CIX0_CSSSP 0x02 551 /* test mode only */ 552 #define ISACSX_CIX0_CSSCP 0x03 553 #define ISACSX_CIX0_CAR8 0x08 554 #define ISACSX_CIX0_CAR10 0x09 555 #define ISACSX_CIX0_CARL 0x0a 556 #define ISACSX_CIX0_CDIU 0x0f 557 558 /* Interrupt, General Configuration Registers */ 559 560 #define ISACSX_ISTA_ST 0x20 561 #define ISACSX_ISTA_CIC 0x10 562 #define ISACSX_ISTA_AUX 0x08 563 #define ISACSX_ISTA_TRAN 0x04 564 #define ISACSX_ISTA_MOS 0x02 565 #define ISACSX_ISTA_ICD 0x01 566 567 #define ISACSX_MASK_ST 0x20 568 #define ISACSX_MASK_CIC 0x10 569 #define ISACSX_MASK_AUX 0x08 570 #define ISACSX_MASK_TRAN 0x04 571 #define ISACSX_MASK_MOS 0x02 572 #define ISACSX_MASK_ICD 0x01 573 574 #define ISACSX_AUXI_EAW 0x20 575 #define ISACSX_AUXI_WOV 0x10 576 #define ISACSX_AUXI_TIN2 0x08 577 #define ISACSX_AUXI_TIN1 0x04 578 579 #define ISACSX_AUXM_EAW 0x20 580 #define ISACSX_AUXM_WOV 0x10 581 #define ISACSX_AUXM_TIN2 0x08 582 #define ISACSX_AUXM_TIN1 0x04 583 584 #define ISACSX_MODE1_WTC1 0x10 585 #define ISACSX_MODE1_WTC2 0x08 586 #define ISACSX_MODE1_CFS 0x04 587 #define ISACSX_MODE1_RSS2 0x02 588 #define ISACSX_MODE1_RSS1 0x01 589 590 #define ISACSX_MODE2_INT_POL 0x08 591 #define ISACSX_MODE2_PPSDX 0x01 592 593 #define ISACSX_ID_MASK 0x2F /* 0x01 = Version 1.3 */ 594 595 596 extern unsigned char isacsx_imaskd; 597 extern unsigned char isacsx_imask; 598 599 #endif /* I4B_ISACSX_H_ */ 600