1 /** $MirOS: src/sys/dev/ic/if_wireg.h,v 1.2 2005/03/06 21:27:40 tg Exp $ */ 2 /* $OpenBSD: if_wireg.h,v 1.34 2004/03/02 21:59:29 millert Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * From: if_wireg.h,v 1.8.2.2 2001/08/25 00:48:25 nsayer Exp $ 36 */ 37 38 #define WI_DELAY 5 39 #define WI_TIMEOUT (500000/WI_DELAY) /* 500ms */ 40 41 #define WI_PORT0 0 42 #define WI_PORT1 1 43 #define WI_PORT2 2 44 #define WI_PORT3 3 45 #define WI_PORT4 4 46 #define WI_PORT5 5 47 48 /* Default port: 0 (only 0 exists on stations) */ 49 #define WI_DEFAULT_PORT (WI_PORT0 << 8) 50 51 /* Default TX rate: 2Mbps, auto fallback */ 52 #define WI_DEFAULT_TX_RATE 3 53 54 /* Default network name (wildcard) */ 55 #define WI_DEFAULT_NETNAME "" 56 57 #define WI_DEFAULT_AP_DENSITY 1 58 59 #define WI_DEFAULT_RTS_THRESH 2347 60 61 #define WI_DEFAULT_DATALEN 2304 62 63 #define WI_DEFAULT_CREATE_IBSS 0 64 65 #define WI_DEFAULT_PM_ENABLED 0 66 67 #define WI_DEFAULT_MAX_SLEEP 100 68 69 #define WI_DEFAULT_NODENAME "WaveLAN/IEEE node" 70 71 #define WI_DEFAULT_IBSS "IBSS" 72 73 #define WI_DEFAULT_CHAN 3 74 75 #define WI_DEFAULT_ROAMING 1 76 77 #define WI_DEFAULT_AUTHTYPE 1 78 79 #define WI_DEFAULT_DIVERSITY 0 80 81 /* 82 * register space access macros 83 */ 84 85 #if defined(__sparc64__) 86 #define WI_BIG_ENDIAN_POSSIBLE (sc->wi_flags & WI_FLAGS_BUS_PCMCIA) 87 #else 88 #define WI_BIG_ENDIAN_POSSIBLE 0 89 #endif 90 91 #define CSR_WRITE_4(sc, reg, val) \ 92 bus_space_write_4(sc->wi_btag, sc->wi_bhandle, \ 93 (sc->sc_pci ? reg * 2: reg), \ 94 WI_BIG_ENDIAN_POSSIBLE ? htole32(val) : (val)) 95 #define CSR_WRITE_2(sc, reg, val) \ 96 bus_space_write_2(sc->wi_btag, sc->wi_bhandle, \ 97 (sc->sc_pci ? reg * 2: reg), \ 98 WI_BIG_ENDIAN_POSSIBLE ? htole16(val) : (val)) 99 #define CSR_WRITE_1(sc, reg, val) \ 100 bus_space_write_1(sc->wi_btag, sc->wi_bhandle, \ 101 (sc->sc_pci ? reg * 2: reg), val) 102 103 #define CSR_READ_4(sc, reg) \ 104 (WI_BIG_ENDIAN_POSSIBLE ? \ 105 letoh32(bus_space_read_4(sc->wi_btag, sc->wi_bhandle, \ 106 (sc->sc_pci ? reg * 2: reg))) : \ 107 bus_space_read_4(sc->wi_btag, sc->wi_bhandle, \ 108 (sc->sc_pci ? reg * 2: reg))) 109 #define CSR_READ_2(sc, reg) \ 110 (WI_BIG_ENDIAN_POSSIBLE ? \ 111 letoh16(bus_space_read_2(sc->wi_btag, sc->wi_bhandle, \ 112 (sc->sc_pci ? reg * 2: reg))) : \ 113 bus_space_read_2(sc->wi_btag, sc->wi_bhandle, \ 114 (sc->sc_pci ? reg * 2: reg))) 115 #define CSR_READ_1(sc, reg) \ 116 bus_space_read_1(sc->wi_btag, sc->wi_bhandle, \ 117 (sc->sc_pci ? reg * 2: reg)) 118 119 #define CSR_READ_RAW_2(sc, ba, dst, sz) \ 120 bus_space_read_raw_multi_2((sc)->wi_btag, \ 121 (sc)->wi_bhandle, \ 122 (sc->sc_pci? ba * 2: ba), (dst), (sz)) 123 #define CSR_WRITE_RAW_2(sc, ba, dst, sz) \ 124 bus_space_write_raw_multi_2((sc)->wi_btag, \ 125 (sc)->wi_bhandle, \ 126 (sc->sc_pci? ba * 2: ba), (dst), (sz)) 127 128 /* 129 * The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent 130 * calls 'Hermes.' In typical fashion, getting documentation about this 131 * controller is about as easy as squeezing blood from a stone. Here 132 * is more or less what I know: 133 * 134 * - The Hermes controller is firmware driven, and the host interacts 135 * with the Hermes via a firmware interface, which can change. 136 * 137 * - The Hermes is described in a document called: "Hermes Firmware 138 * WaveLAN/IEEE Station Functions," document #010245, which of course 139 * Lucent will not release without an NDA. 140 * 141 * - Lucent has created a library called HCF (Hardware Control Functions) 142 * though which it wants developers to interact with the card. The HCF 143 * is needlessly complex, ill conceived and badly documented. Actually, 144 * the comments in the HCP code itself aren't bad, but the publicly 145 * available manual that comes with it is awful, probably due largely to 146 * the fact that it has been emasculated in order to hide information 147 * that Lucent wants to keep proprietary. The purpose of the HCF seems 148 * to be to insulate the driver programmer from the Hermes itself so that 149 * Lucent has an excuse not to release programming in for it. 150 * 151 * - Lucent only makes available documentation and code for 'HCF Light' 152 * which is a stripped down version of HCF with certain features not 153 * implemented, most notably support for 802.11 frames. 154 * 155 * - The HCF code which I have seen blows goats. Whoever decided to 156 * use a 132 column format should be shot. 157 * 158 * Rather than actually use the Lucent HCF library, I have stripped all 159 * the useful information from it and used it to create a driver in the 160 * usual BSD form. Note: I don't want to hear anybody whining about the 161 * fact that the Lucent code is GPLed and mine isn't. I did not actually 162 * put any of Lucent's code in this driver: I only used it as a reference 163 * to obtain information about the underlying hardware. The Hermes 164 * programming interface is not GPLed, so bite me. 165 */ 166 167 /* 168 * Size of Hermes & Prism2 I/O space. 169 */ 170 #define WI_IOSIZ 0x40 171 172 /* 173 * Hermes register definitions and what little I know about them. 174 */ 175 176 /* Hermes command/status registers. */ 177 #define WI_COMMAND 0x00 178 #define WI_PARAM0 0x02 179 #define WI_PARAM1 0x04 180 #define WI_PARAM2 0x06 181 #define WI_STATUS 0x08 182 #define WI_RESP0 0x0A 183 #define WI_RESP1 0x0C 184 #define WI_RESP2 0x0E 185 186 /* Command register values. */ 187 #define WI_CMD_BUSY 0x8000 /* busy bit */ 188 #define WI_CMD_INI 0x0000 /* initialize */ 189 #define WI_CMD_ENABLE 0x0001 /* enable */ 190 #define WI_CMD_DISABLE 0x0002 /* disable */ 191 #define WI_CMD_DIAG 0x0003 192 #define WI_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */ 193 #define WI_CMD_TX 0x000B /* transmit */ 194 #define WI_CMD_NOTIFY 0x0010 195 #define WI_CMD_INQUIRE 0x0011 196 #define WI_CMD_ACCESS 0x0021 197 #define WI_CMD_PROGRAM 0x0022 198 199 #define WI_CMD_CODE_MASK 0x003F 200 201 /* 202 * Reclaim qualifier bit, applicable to the 203 * TX and INQUIRE commands. 204 */ 205 #define WI_RECLAIM 0x0100 /* reclaim NIC memory */ 206 207 /* 208 * ACCESS command qualifier bits. 209 */ 210 #define WI_ACCESS_READ 0x0000 211 #define WI_ACCESS_WRITE 0x0100 212 213 /* 214 * PROGRAM command qualifier bits. 215 */ 216 #define WI_PROGRAM_DISABLE 0x0000 217 #define WI_PROGRAM_ENABLE_RAM 0x0100 218 #define WI_PROGRAM_ENABLE_NVRAM 0x0200 219 #define WI_PROGRAM_NVRAM 0x0300 220 221 /* Status register values */ 222 #define WI_STAT_CMD_CODE 0x003F 223 #define WI_STAT_DIAG_ERR 0x0100 224 #define WI_STAT_INQ_ERR 0x0500 225 #define WI_STAT_CMD_RESULT 0x7F00 226 227 /* memory handle management registers */ 228 #define WI_INFO_FID 0x10 229 #define WI_RX_FID 0x20 230 #define WI_ALLOC_FID 0x22 231 #define WI_TX_CMP_FID 0x24 232 233 /* 234 * Buffer Access Path (BAP) registers. 235 * These are I/O channels. I believe you can use each one for 236 * any desired purpose independently of the other. In general 237 * though, we use BAP1 for reading and writing LTV records and 238 * reading received data frames, and BAP0 for writing transmit 239 * frames. This is a convention though, not a rule. 240 */ 241 #define WI_SEL0 0x18 242 #define WI_SEL1 0x1A 243 #define WI_OFF0 0x1C 244 #define WI_OFF1 0x1E 245 #define WI_DATA0 0x36 246 #define WI_DATA1 0x38 247 #define WI_BAP0 WI_DATA0 248 #define WI_BAP1 WI_DATA1 249 250 #define WI_OFF_BUSY 0x8000 251 #define WI_OFF_ERR 0x4000 252 #define WI_OFF_DATAOFF 0x0FFF 253 254 /* Event registers */ 255 #define WI_EVENT_STAT 0x30 /* Event status */ 256 #define WI_INT_EN 0x32 /* Interrupt enable/disable */ 257 #define WI_EVENT_ACK 0x34 /* Ack event */ 258 259 /* Events */ 260 #define WI_EV_TICK 0x8000 /* aux timer tick */ 261 #define WI_EV_RES 0x4000 /* controller h/w error (time out) */ 262 #define WI_EV_INFO_DROP 0x2000 /* no RAM to build unsolicited frame */ 263 #define WI_EV_NO_CARD 0x0800 /* card removed (hunh?) */ 264 #define WI_EV_DUIF_RX 0x0400 /* wavelan management packet received */ 265 #define WI_EV_INFO 0x0080 /* async info frame */ 266 #define WI_EV_CMD 0x0010 /* command completed */ 267 #define WI_EV_ALLOC 0x0008 /* async alloc/reclaim completed */ 268 #define WI_EV_TX_EXC 0x0004 /* async xmit completed with failure */ 269 #define WI_EV_TX 0x0002 /* async xmit completed successfully */ 270 #define WI_EV_RX 0x0001 /* async rx completed */ 271 272 #define WI_INTRS \ 273 (WI_EV_RX|WI_EV_TX|WI_EV_TX_EXC|WI_EV_ALLOC|WI_EV_INFO|WI_EV_INFO_DROP) 274 275 /* Host software registers */ 276 #define WI_SW0 0x28 277 #define WI_SW1 0x2A 278 #define WI_SW2 0x2C 279 #define WI_SW3 0x2E 280 281 #define WI_CNTL 0x14 282 283 #define WI_CNTL_AUX_ENA 0xC000 284 #define WI_CNTL_AUX_ENA_STAT 0xC000 285 #define WI_CNTL_AUX_DIS_STAT 0x0000 286 #define WI_CNTL_AUX_ENA_CNTL 0x8000 287 #define WI_CNTL_AUX_DIS_CNTL 0x4000 288 289 #define WI_AUX_PAGE 0x3A 290 #define WI_AUX_OFFSET 0x3C 291 #define WI_AUX_DATA 0x3E 292 293 #define WI_COR_OFFSET 0x40 /* COR attribute offset of card */ 294 #define WI_COR_IOMODE 0x41 /* Enable i/o mode with level irqs */ 295 296 #define WI_PLX_LOCALRES 0x14 /* PLX chip's local registers */ 297 #define WI_PLX_MEMRES 0x18 /* Prism attribute memory (PLX) */ 298 #define WI_PLX_IORES 0x1C /* Prism I/O space (PLX) */ 299 #define WI_PLX_INTCSR 0x4C /* PLX Interrupt CSR */ 300 #define WI_PLX_INTEN 0x40 /* PCI Interrupt Enable bit */ 301 #define WI_PLX_LINT1STAT 0x04 /* Local interrupt 1 status bit */ 302 #define WI_PLX_COR_OFFSET 0x3E0 /* COR attribute offset of card */ 303 304 #define WI_ACEX_CMDRES 0x10 /* BAR0 (I/O) for ACEX-based bridge */ 305 #define WI_ACEX_LOCALRES 0x14 /* BAR1 (I/O) for ACEX-based bridge */ 306 #define WI_ACEX_IORES 0x18 /* BAR2 (I/O) for ACEX-based bridge */ 307 #define WI_ACEX_COR_OFFSET 0xe0 /* COR attribute offset of card */ 308 309 #define WI_TMD_LOCALRES 0x14 /* TMD chip's local registers */ 310 #define WI_TMD_IORES 0x18 /* Prism I/O space (TMD) */ 311 312 #define WI_DRVR_MAGIC 0x4A2D /* Magic number for card detection */ 313 314 /* 315 * PCI Host Interface Registers (HFA3842 Specific) 316 * The value of all Register's Offset, such as WI_INFO_FID and WI_PARAM0, 317 * has doubled. 318 * About WI_PCI_COR: In this Register, only soft-reset bit implement; Bit(7). 319 */ 320 #define WI_PCI_CBMA 0x10 321 #define WI_PCI_COR_OFFSET 0x4C 322 #define WI_PCI_HCR 0x5C 323 #define WI_PCI_MASTER0_ADDRH 0x80 324 #define WI_PCI_MASTER0_ADDRL 0x84 325 #define WI_PCI_MASTER0_LEN 0x88 326 #define WI_PCI_MASTER0_CON 0x8C 327 328 #define WI_PCI_STATUS 0x98 329 330 #define WI_PCI_MASTER1_ADDRH 0xA0 331 #define WI_PCI_MASTER1_ADDRL 0xA4 332 #define WI_PCI_MASTER1_LEN 0xA8 333 #define WI_PCI_MASTER1_CON 0xAC 334 335 #define WI_COR_SOFT_RESET (1 << 7) 336 #define WI_COR_CLEAR 0x00 337 338 /* 339 * One form of communication with the Hermes is with what Lucent calls 340 * LTV records, where LTV stands for Length, Type and Value. The length 341 * and type are 16 bits and are in native byte order. The value is in 342 * multiples of 16 bits and is in little endian byte order. 343 */ 344 struct wi_ltv_gen { 345 u_int16_t wi_len; 346 u_int16_t wi_type; 347 u_int16_t wi_val; 348 }; 349 350 struct wi_ltv_str { 351 u_int16_t wi_len; 352 u_int16_t wi_type; 353 u_int16_t wi_str[17]; 354 }; 355 356 #define WI_SETVAL(recno, val) \ 357 do { \ 358 struct wi_ltv_gen g; \ 359 \ 360 g.wi_len = 2; \ 361 g.wi_type = recno; \ 362 g.wi_val = htole16(val); \ 363 wi_write_record(sc, &g); \ 364 } while (0) 365 366 #define WI_SETSTR(recno, str) \ 367 do { \ 368 struct wi_ltv_str s; \ 369 int l; \ 370 \ 371 l = (str.i_len + 1) & ~0x1; \ 372 bzero((char *)&s, sizeof(s)); \ 373 s.wi_len = (l / 2) + 2; \ 374 s.wi_type = recno; \ 375 s.wi_str[0] = htole16(str.i_len); \ 376 memmove(&s.wi_str[1], str.i_nwid, str.i_len); \ 377 wi_write_record(sc, (struct wi_ltv_gen *)&s); \ 378 } while (0) 379 380 /* 381 * Download buffer location and length (0xFD01). 382 */ 383 #define WI_RID_DNLD_BUF 0xFD01 384 struct wi_ltv_dnld_buf { 385 u_int16_t wi_len; 386 u_int16_t wi_type; 387 u_int16_t wi_buf_pg; /* page addr of intermediate dl buf*/ 388 u_int16_t wi_buf_off; /* offset of idb */ 389 u_int16_t wi_buf_len; /* len of idb */ 390 }; 391 392 /* 393 * Mem sizes (0xFD02). 394 */ 395 #define WI_RID_MEMSZ 0xFD02 396 struct wi_ltv_memsz { 397 u_int16_t wi_len; 398 u_int16_t wi_type; 399 u_int16_t wi_mem_ram; 400 u_int16_t wi_mem_nvram; 401 }; 402 403 /* 404 * NIC Identification (0xFD0B == WI_RID_CARD_ID) 405 */ 406 struct wi_ltv_ver { 407 u_int16_t wi_len; 408 u_int16_t wi_type; 409 u_int16_t wi_ver[4]; 410 }; 411 412 /* 413 * List of intended regulatory domains (WI_RID_DOMAINS = 0xFD11). 414 */ 415 struct wi_ltv_domains { 416 u_int16_t wi_len; 417 u_int16_t wi_type; 418 u_int16_t wi_domains[6]; 419 }; 420 421 /* 422 * CIS struct (0xFD13 == WI_RID_CIS). 423 */ 424 struct wi_ltv_cis { 425 u_int16_t wi_len; 426 u_int16_t wi_type; 427 u_int16_t wi_cis[240]; 428 }; 429 430 /* 431 * Communications quality (0xFD43 == WI_RID_COMMQUAL). 432 */ 433 struct wi_ltv_commqual { 434 u_int16_t wi_len; 435 u_int16_t wi_type; 436 u_int16_t wi_coms_qual; 437 u_int16_t wi_sig_lvl; 438 u_int16_t wi_noise_lvl; 439 }; 440 441 /* 442 * Actual system scale thresholds (0xFD46 == WI_RID_SCALETHRESH). 443 */ 444 struct wi_ltv_scalethresh { 445 u_int16_t wi_len; 446 u_int16_t wi_type; 447 u_int16_t wi_energy_detect; 448 u_int16_t wi_carrier_detect; 449 u_int16_t wi_defer; 450 u_int16_t wi_cell_search; 451 u_int16_t wi_out_of_range; 452 u_int16_t wi_delta_snr; 453 }; 454 455 /* 456 * PCF info struct (0xFD87 == WI_RID_PCF). 457 */ 458 struct wi_ltv_pcf { 459 u_int16_t wi_len; 460 u_int16_t wi_type; 461 u_int16_t wi_energy_detect; 462 u_int16_t wi_carrier_detect; 463 u_int16_t wi_defer; 464 u_int16_t wi_cell_search; 465 u_int16_t wi_range; 466 }; 467 468 /* 469 * Connection control characteristics (0xFC00 == WI_RID_PORTTYPE). 470 * 1 == Basic Service Set (BSS) 471 * 2 == Wireless Distribution System (WDS) 472 * 3 == Pseudo IBSS (aka ad-hoc demo) 473 * 4 == IBSS 474 */ 475 #define WI_PORTTYPE_BSS 0x1 476 #define WI_PORTTYPE_WDS 0x2 477 #define WI_PORTTYPE_ADHOC 0x3 478 #define WI_PORTTYPE_IBSS 0x4 479 #define WI_PORTTYPE_HOSTAP 0x6 480 481 /* 482 * Mac addresses. 483 */ 484 struct wi_ltv_macaddr { 485 u_int16_t wi_len; 486 u_int16_t wi_type; 487 u_int16_t wi_mac_addr[3]; 488 }; 489 490 /* 491 * Station set identification (SSID). 492 */ 493 struct wi_ltv_ssid { 494 u_int16_t wi_len; 495 u_int16_t wi_type; 496 u_int16_t wi_id[17]; 497 }; 498 499 /* 500 * Set our station name (0xFC0E == WI_RID_NODENAME). 501 */ 502 struct wi_ltv_nodename { 503 u_int16_t wi_len; 504 u_int16_t wi_type; 505 u_int16_t wi_nodename[17]; 506 }; 507 508 /* 509 * Multicast addresses to be put in filter. We're allowed up 510 * to 16 addresses in the filter (0xFC80 == WI_RID_MCAST). 511 */ 512 struct wi_ltv_mcast { 513 u_int16_t wi_len; 514 u_int16_t wi_type; 515 struct ether_addr wi_mcast[16]; 516 }; 517 518 /* 519 * Supported rates. 520 */ 521 #define WI_SUPPRATES_1M 0x0001 522 #define WI_SUPPRATES_2M 0x0002 523 #define WI_SUPPRATES_5M 0x0004 524 #define WI_SUPPRATES_11M 0x0008 525 #define WI_RATES_BITS "\20\0011M\0022M\0035.5M\00411M" 526 527 /* 528 * Information frame types. 529 */ 530 #define WI_INFO_NOTIFY 0xF000 /* Handover address */ 531 #define WI_INFO_COUNTERS 0xF100 /* Statistics counters */ 532 #define WI_INFO_SCAN_RESULTS 0xF101 /* Scan results */ 533 #define WI_INFO_LINK_STAT 0xF200 /* Link status */ 534 #define WI_INFO_ASSOC_STAT 0xF201 /* Association status */ 535 536 /* 537 * Hermes transmit/receive frame structure 538 */ 539 struct wi_frame { 540 u_int16_t wi_status; /* 0x00 */ 541 u_int16_t wi_rsvd0; /* 0x02 */ 542 u_int16_t wi_rsvd1; /* 0x04 */ 543 u_int16_t wi_q_info; /* 0x06 */ 544 u_int16_t wi_rsvd2; /* 0x08 */ 545 u_int8_t wi_tx_rtry; /* 0x0A */ 546 u_int8_t wi_tx_rate; /* 0x0A */ 547 u_int16_t wi_tx_ctl; /* 0x0C */ 548 u_int16_t wi_frame_ctl; /* 0x0E */ 549 u_int16_t wi_id; /* 0x10 */ 550 u_int8_t wi_addr1[6]; /* 0x12 */ 551 u_int8_t wi_addr2[6]; /* 0x18 */ 552 u_int8_t wi_addr3[6]; /* 0x1E */ 553 u_int16_t wi_seq_ctl; /* 0x24 */ 554 u_int8_t wi_addr4[6]; /* 0x26 */ 555 u_int16_t wi_dat_len; /* 0x2C */ 556 u_int8_t wi_dst_addr[6]; /* 0x2E */ 557 u_int8_t wi_src_addr[6]; /* 0x34 */ 558 u_int16_t wi_len; /* 0x3A */ 559 u_int16_t wi_dat[3]; /* 0x3C */ /* SNAP header */ 560 u_int16_t wi_type; /* 0x42 */ 561 }; 562 563 #define WI_802_3_OFFSET 0x2E 564 #define WI_802_11_OFFSET 0x44 565 #define WI_802_11_OFFSET_RAW 0x3C 566 #define WI_802_11_OFFSET_HDR 0x0E 567 568 #define WI_STAT_BADCRC 0x0001 569 #define WI_STAT_UNDECRYPTABLE 0x0002 570 #define WI_STAT_ERRSTAT 0x0003 571 #define WI_STAT_MAC_PORT 0x0700 572 #define WI_STAT_1042 0x2000 /* RFC1042 encoded */ 573 #define WI_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */ 574 #define WI_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */ 575 #define WI_STAT_MGMT 0x8000 /* 802.11b management frames */ 576 #define WI_RXSTAT_MSG_TYPE 0xE000 577 578 #define WI_ENC_TX_802_3 0x00 579 #define WI_ENC_TX_802_11 0x11 580 #define WI_ENC_TX_MGMT 0x08 581 #define WI_ENC_TX_E_II 0x0E 582 583 #define WI_ENC_TX_1042 0x00 584 #define WI_ENC_TX_TUNNEL 0xF8 585 586 #define WI_TXCNTL_MACPORT 0x00FF 587 #define WI_TXCNTL_STRUCTTYPE 0xFF00 588 #define WI_TXCNTL_TX_EX 0x0004 589 #define WI_TXCNTL_TX_OK 0x0002 590 #define WI_TXCNTL_NOCRYPT 0x0080 591 592 593 /* 594 * SNAP (sub-network access protocol) constants for transmission 595 * of IP datagrams over IEEE 802 networks, taken from RFC1042. 596 * We need these for the LLC/SNAP header fields in the TX/RX frame 597 * structure. 598 */ 599 #define WI_SNAP_K1 0xaa /* assigned global SAP for SNAP */ 600 #define WI_SNAP_K2 0x00 601 #define WI_SNAP_CONTROL 0x03 /* unnumbered information format */ 602 #define WI_SNAP_WORD0 (WI_SNAP_K1 | (WI_SNAP_K1 << 8)) 603 #define WI_SNAP_WORD1 (WI_SNAP_K2 | (WI_SNAP_CONTROL << 8)) 604 #define WI_SNAPHDR_LEN 0x6 605 #define WI_FCS_LEN 0x4 606 607 #define WI_ETHERTYPE_LEN 0x2 608