1 /* $OpenBSD: if_skreg.h,v 1.16 2005/03/14 01:15:14 brad Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_skreg.h,v 1.9 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 55 * but internally it has a 16K register space. This 16K space is 56 * divided into 128-byte blocks. The first 128 bytes of the I/O 57 * window represent the first block, which is permanently mapped 58 * at the start of the window. The other 127 blocks can be mapped 59 * to the second 128 bytes of the I/O window by setting the desired 60 * block value in the RAP register in block 0. Not all of the 127 61 * blocks are actually used. Most registers are 32 bits wide, but 62 * there are a few 16-bit and 8-bit ones as well. 63 */ 64 65 66 /* Start of remappable register window. */ 67 #define SK_WIN_BASE 0x0080 68 69 /* Size of a window */ 70 #define SK_WIN_LEN 0x80 71 72 #define SK_WIN_MASK 0x3F80 73 #define SK_REG_MASK 0x7F 74 75 /* Compute the window of a given register (for the RAP register) */ 76 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 77 78 /* Compute the relative offset of a register within the window */ 79 #define SK_REG(reg) ((reg) & SK_REG_MASK) 80 81 #define SK_PORT_A 0 82 #define SK_PORT_B 1 83 84 /* 85 * Compute offset of port-specific register. Since there are two 86 * ports, there are two of some GEnesis modules (e.g. two sets of 87 * DMA queues, two sets of FIFO control registers, etc...). Normally, 88 * the block for port 0 is at offset 0x0 and the block for port 1 is 89 * at offset 0x80 (i.e. the next page over). However for the transmit 90 * BMUs and RAMbuffers, there are two blocks for each port: one for 91 * the sync transmit queue and one for the async queue (which we don't 92 * use). However instead of ordering them like this: 93 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 94 * SysKonnect has instead ordered them like this: 95 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 96 * This means that when referencing the TX BMU and RAMbuffer registers, 97 * we have to double the block offset (0x80 * 2) in order to reach the 98 * second queue. This prevents us from using the same formula 99 * (sk_port * 0x80) to compute the offsets for all of the port-specific 100 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 101 * The simplest thing is to provide an extra argument to these macros: 102 * the 'skip' parameter. The 'skip' value is the number of extra pages 103 * for skip when computing the port0/port1 offsets. For most registers, 104 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 105 */ 106 #define SK_IF_READ_4(sc_if, skip, reg) \ 107 sk_win_read_4(sc_if->sk_softc, reg + \ 108 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 109 #define SK_IF_READ_2(sc_if, skip, reg) \ 110 sk_win_read_2(sc_if->sk_softc, reg + \ 111 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 112 #define SK_IF_READ_1(sc_if, skip, reg) \ 113 sk_win_read_1(sc_if->sk_softc, reg + \ 114 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 115 116 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 117 sk_win_write_4(sc_if->sk_softc, \ 118 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 119 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 120 sk_win_write_2(sc_if->sk_softc, \ 121 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 122 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 123 sk_win_write_1(sc_if->sk_softc, \ 124 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 125 126 /* Block 0 registers, permanently mapped at iobase. */ 127 #define SK_RAP 0x0000 128 #define SK_CSR 0x0004 129 #define SK_LED 0x0006 130 #define SK_ISR 0x0008 /* interrupt source */ 131 #define SK_IMR 0x000C /* interrupt mask */ 132 #define SK_IESR 0x0010 /* interrupt hardware error source */ 133 #define SK_IEMR 0x0014 /* interrupt hardware error mask */ 134 #define SK_ISSR 0x0018 /* special interrupt source */ 135 #define SK_XM_IMR0 0x0020 136 #define SK_XM_ISR0 0x0028 137 #define SK_XM_PHYADDR0 0x0030 138 #define SK_XM_PHYDATA0 0x0034 139 #define SK_XM_IMR1 0x0040 140 #define SK_XM_ISR1 0x0048 141 #define SK_XM_PHYADDR1 0x0050 142 #define SK_XM_PHYDATA1 0x0054 143 #define SK_BMU_RX_CSR0 0x0060 144 #define SK_BMU_RX_CSR1 0x0064 145 #define SK_BMU_TXS_CSR0 0x0068 146 #define SK_BMU_TXA_CSR0 0x006C 147 #define SK_BMU_TXS_CSR1 0x0070 148 #define SK_BMU_TXA_CSR1 0x0074 149 150 /* SK_CSR register */ 151 #define SK_CSR_SW_RESET 0x0001 152 #define SK_CSR_SW_UNRESET 0x0002 153 #define SK_CSR_MASTER_RESET 0x0004 154 #define SK_CSR_MASTER_UNRESET 0x0008 155 #define SK_CSR_MASTER_STOP 0x0010 156 #define SK_CSR_MASTER_DONE 0x0020 157 #define SK_CSR_SW_IRQ_CLEAR 0x0040 158 #define SK_CSR_SW_IRQ_SET 0x0080 159 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 160 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 MHz, = 33 */ 161 162 /* SK_LED register */ 163 #define SK_LED_GREEN_OFF 0x01 164 #define SK_LED_GREEN_ON 0x02 165 166 /* SK_ISR register */ 167 #define SK_ISR_TX2_AS_CHECK 0x00000001 168 #define SK_ISR_TX2_AS_EOF 0x00000002 169 #define SK_ISR_TX2_AS_EOB 0x00000004 170 #define SK_ISR_TX2_S_CHECK 0x00000008 171 #define SK_ISR_TX2_S_EOF 0x00000010 172 #define SK_ISR_TX2_S_EOB 0x00000020 173 #define SK_ISR_TX1_AS_CHECK 0x00000040 174 #define SK_ISR_TX1_AS_EOF 0x00000080 175 #define SK_ISR_TX1_AS_EOB 0x00000100 176 #define SK_ISR_TX1_S_CHECK 0x00000200 177 #define SK_ISR_TX1_S_EOF 0x00000400 178 #define SK_ISR_TX1_S_EOB 0x00000800 179 #define SK_ISR_RX2_CHECK 0x00001000 180 #define SK_ISR_RX2_EOF 0x00002000 181 #define SK_ISR_RX2_EOB 0x00004000 182 #define SK_ISR_RX1_CHECK 0x00008000 183 #define SK_ISR_RX1_EOF 0x00010000 184 #define SK_ISR_RX1_EOB 0x00020000 185 #define SK_ISR_LINK2_OFLOW 0x00040000 186 #define SK_ISR_MAC2 0x00080000 187 #define SK_ISR_LINK1_OFLOW 0x00100000 188 #define SK_ISR_MAC1 0x00200000 189 #define SK_ISR_TIMER 0x00400000 190 #define SK_ISR_EXTERNAL_REG 0x00800000 191 #define SK_ISR_SW 0x01000000 192 #define SK_ISR_I2C_RDY 0x02000000 193 #define SK_ISR_TX2_TIMEO 0x04000000 194 #define SK_ISR_TX1_TIMEO 0x08000000 195 #define SK_ISR_RX2_TIMEO 0x10000000 196 #define SK_ISR_RX1_TIMEO 0x20000000 197 #define SK_ISR_RSVD 0x40000000 198 #define SK_ISR_HWERR 0x80000000 199 200 /* SK_IMR register */ 201 #define SK_IMR_TX2_AS_CHECK 0x00000001 202 #define SK_IMR_TX2_AS_EOF 0x00000002 203 #define SK_IMR_TX2_AS_EOB 0x00000004 204 #define SK_IMR_TX2_S_CHECK 0x00000008 205 #define SK_IMR_TX2_S_EOF 0x00000010 206 #define SK_IMR_TX2_S_EOB 0x00000020 207 #define SK_IMR_TX1_AS_CHECK 0x00000040 208 #define SK_IMR_TX1_AS_EOF 0x00000080 209 #define SK_IMR_TX1_AS_EOB 0x00000100 210 #define SK_IMR_TX1_S_CHECK 0x00000200 211 #define SK_IMR_TX1_S_EOF 0x00000400 212 #define SK_IMR_TX1_S_EOB 0x00000800 213 #define SK_IMR_RX2_CHECK 0x00001000 214 #define SK_IMR_RX2_EOF 0x00002000 215 #define SK_IMR_RX2_EOB 0x00004000 216 #define SK_IMR_RX1_CHECK 0x00008000 217 #define SK_IMR_RX1_EOF 0x00010000 218 #define SK_IMR_RX1_EOB 0x00020000 219 #define SK_IMR_LINK2_OFLOW 0x00040000 220 #define SK_IMR_MAC2 0x00080000 221 #define SK_IMR_LINK1_OFLOW 0x00100000 222 #define SK_IMR_MAC1 0x00200000 223 #define SK_IMR_TIMER 0x00400000 224 #define SK_IMR_EXTERNAL_REG 0x00800000 225 #define SK_IMR_SW 0x01000000 226 #define SK_IMR_I2C_RDY 0x02000000 227 #define SK_IMR_TX2_TIMEO 0x04000000 228 #define SK_IMR_TX1_TIMEO 0x08000000 229 #define SK_IMR_RX2_TIMEO 0x10000000 230 #define SK_IMR_RX1_TIMEO 0x20000000 231 #define SK_IMR_RSVD 0x40000000 232 #define SK_IMR_HWERR 0x80000000 233 234 #define SK_INTRS1 \ 235 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 236 237 #define SK_INTRS2 \ 238 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 239 240 /* SK_IESR register */ 241 #define SK_IESR_PAR_RX2 0x00000001 242 #define SK_IESR_PAR_RX1 0x00000002 243 #define SK_IESR_PAR_MAC2 0x00000004 244 #define SK_IESR_PAR_MAC1 0x00000008 245 #define SK_IESR_PAR_WR_RAM 0x00000010 246 #define SK_IESR_PAR_RD_RAM 0x00000020 247 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040 248 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080 249 #define SK_IESR_NO_STS_MAC2 0x00000100 250 #define SK_IESR_NO_STS_MAC1 0x00000200 251 #define SK_IESR_IRQ_STS 0x00000400 252 #define SK_IESR_MASTERERR 0x00000800 253 254 /* SK_IEMR register */ 255 #define SK_IEMR_PAR_RX2 0x00000001 256 #define SK_IEMR_PAR_RX1 0x00000002 257 #define SK_IEMR_PAR_MAC2 0x00000004 258 #define SK_IEMR_PAR_MAC1 0x00000008 259 #define SK_IEMR_PAR_WR_RAM 0x00000010 260 #define SK_IEMR_PAR_RD_RAM 0x00000020 261 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 262 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 263 #define SK_IEMR_NO_STS_MAC2 0x00000100 264 #define SK_IEMR_NO_STS_MAC1 0x00000200 265 #define SK_IEMR_IRQ_STS 0x00000400 266 #define SK_IEMR_MASTERERR 0x00000800 267 268 /* Block 2 */ 269 #define SK_MAC0_0 0x0100 270 #define SK_MAC0_1 0x0104 271 #define SK_MAC1_0 0x0108 272 #define SK_MAC1_1 0x010C 273 #define SK_MAC2_0 0x0110 274 #define SK_MAC2_1 0x0114 275 #define SK_CONNTYPE 0x0118 276 #define SK_PMDTYPE 0x0119 277 #define SK_CONFIG 0x011A 278 #define SK_CHIPVER 0x011B 279 #define SK_EPROM0 0x011C 280 #define SK_EPROM1 0x011D 281 #define SK_EPROM2 0x011E 282 #define SK_EPROM3 0x011F 283 #define SK_EP_ADDR 0x0120 284 #define SK_EP_DATA 0x0124 285 #define SK_EP_LOADCTL 0x0128 286 #define SK_EP_LOADTST 0x0129 287 #define SK_TIMERINIT 0x0130 288 #define SK_TIMER 0x0134 289 #define SK_TIMERCTL 0x0138 290 #define SK_TIMERTST 0x0139 291 #define SK_IMTIMERINIT 0x0140 292 #define SK_IMTIMER 0x0144 293 #define SK_IMTIMERCTL 0x0148 294 #define SK_IMTIMERTST 0x0149 295 #define SK_IMMR 0x014C 296 #define SK_IHWEMR 0x0150 297 #define SK_TESTCTL1 0x0158 298 #define SK_TESTCTL2 0x0159 299 #define SK_GPIO 0x015C 300 #define SK_I2CHWCTL 0x0160 301 #define SK_I2CHWDATA 0x0164 302 #define SK_I2CHWIRQ 0x0168 303 #define SK_I2CSW 0x016C 304 #define SK_BLNKINIT 0x0170 305 #define SK_BLNKCOUNT 0x0174 306 #define SK_BLNKCTL 0x0178 307 #define SK_BLNKSTS 0x0179 308 #define SK_BLNKTST 0x017A 309 310 /* Values for SK_CHIPVER */ 311 #define SK_GENESIS 0x0A 312 #define SK_YUKON 0xB0 313 #define SK_YUKON_LITE 0xB1 314 #define SK_YUKON_LP 0xB2 315 #define SK_YUKON_XL 0xB3 316 #define SK_YUKON_EC 0xB6 317 #define SK_YUKON_FE 0xB7 318 319 #define SK_YUKON_FAMILY(x) ((x) & 0xB0) 320 321 /* Known revisions in SK_CONFIG */ 322 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach */ 323 #define SK_YUKON_LITE_REV_A1 0x3 324 #define SK_YUKON_LITE_REV_A3 0x7 325 326 #define SK_YUKON_EC_REV_A1 0x0 327 #define SK_YUKON_EC_REV_A2 0x1 328 #define SK_YUKON_EC_REV_A3 0x2 329 330 #define SK_IMCTL_STOP 0x02 331 #define SK_IMCTL_START 0x04 332 333 #define SK_IMTIMER_TICKS 54 334 #define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 335 336 /* 337 * The SK_EPROM0 register contains a byte that describes the 338 * amount of SRAM mounted on the NIC. The value also tells if 339 * the chips are 64K or 128K. This affects the RAMbuffer address 340 * offset that we need to use. 341 */ 342 #define SK_RAMSIZE_512K_64 0x1 343 #define SK_RAMSIZE_1024K_128 0x2 344 #define SK_RAMSIZE_1024K_64 0x3 345 #define SK_RAMSIZE_2048K_128 0x4 346 347 #define SK_RBOFF_0 0x0 348 #define SK_RBOFF_80000 0x80000 349 350 /* 351 * SK_EEPROM1 contains the PHY type, which may be XMAC for 352 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 353 * PHY. 354 */ 355 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 356 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 357 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 358 #define SK_PHYTYPE_NAT 3 /* National DP83891 */ 359 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 360 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 361 362 /* 363 * PHY addresses. 364 */ 365 #define SK_PHYADDR_XMAC 0x0 366 #define SK_PHYADDR_BCOM 0x1 367 #define SK_PHYADDR_LONE 0x3 368 #define SK_PHYADDR_NAT 0x0 369 #define SK_PHYADDR_MARV 0x0 370 371 #define SK_CONFIG_SINGLEMAC 0x01 372 #define SK_CONFIG_DIS_DSL_CLK 0x02 373 374 #define SK_PMD_1000BASELX 0x4C 375 #define SK_PMD_1000BASESX 0x53 376 #define SK_PMD_1000BASECX 0x43 377 #define SK_PMD_1000BASETX 0x54 378 379 /* GPIO bits */ 380 #define SK_GPIO_DAT0 0x00000001 381 #define SK_GPIO_DAT1 0x00000002 382 #define SK_GPIO_DAT2 0x00000004 383 #define SK_GPIO_DAT3 0x00000008 384 #define SK_GPIO_DAT4 0x00000010 385 #define SK_GPIO_DAT5 0x00000020 386 #define SK_GPIO_DAT6 0x00000040 387 #define SK_GPIO_DAT7 0x00000080 388 #define SK_GPIO_DAT8 0x00000100 389 #define SK_GPIO_DAT9 0x00000200 390 #define SK_GPIO_DIR0 0x00010000 391 #define SK_GPIO_DIR1 0x00020000 392 #define SK_GPIO_DIR2 0x00040000 393 #define SK_GPIO_DIR3 0x00080000 394 #define SK_GPIO_DIR4 0x00100000 395 #define SK_GPIO_DIR5 0x00200000 396 #define SK_GPIO_DIR6 0x00400000 397 #define SK_GPIO_DIR7 0x00800000 398 #define SK_GPIO_DIR8 0x01000000 399 #define SK_GPIO_DIR9 0x02000000 400 401 /* Block 3 Ram interface and MAC arbiter registers */ 402 #define SK_RAMADDR 0x0180 403 #define SK_RAMDATA0 0x0184 404 #define SK_RAMDATA1 0x0188 405 #define SK_TO0 0x0190 406 #define SK_TO1 0x0191 407 #define SK_TO2 0x0192 408 #define SK_TO3 0x0193 409 #define SK_TO4 0x0194 410 #define SK_TO5 0x0195 411 #define SK_TO6 0x0196 412 #define SK_TO7 0x0197 413 #define SK_TO8 0x0198 414 #define SK_TO9 0x0199 415 #define SK_TO10 0x019A 416 #define SK_TO11 0x019B 417 #define SK_RITIMEO_TMR 0x019C 418 #define SK_RAMCTL 0x01A0 419 #define SK_RITIMER_TST 0x01A2 420 421 #define SK_RAMCTL_RESET 0x0001 422 #define SK_RAMCTL_UNRESET 0x0002 423 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 424 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 425 426 /* Mac arbiter registers */ 427 #define SK_MINIT_RX1 0x01B0 428 #define SK_MINIT_RX2 0x01B1 429 #define SK_MINIT_TX1 0x01B2 430 #define SK_MINIT_TX2 0x01B3 431 #define SK_MTIMEO_RX1 0x01B4 432 #define SK_MTIMEO_RX2 0x01B5 433 #define SK_MTIMEO_TX1 0x01B6 434 #define SK_MTIEMO_TX2 0x01B7 435 #define SK_MACARB_CTL 0x01B8 436 #define SK_MTIMER_TST 0x01BA 437 #define SK_RCINIT_RX1 0x01C0 438 #define SK_RCINIT_RX2 0x01C1 439 #define SK_RCINIT_TX1 0x01C2 440 #define SK_RCINIT_TX2 0x01C3 441 #define SK_RCTIMEO_RX1 0x01C4 442 #define SK_RCTIMEO_RX2 0x01C5 443 #define SK_RCTIMEO_TX1 0x01C6 444 #define SK_RCTIMEO_TX2 0x01C7 445 #define SK_RECOVERY_CTL 0x01C8 446 #define SK_RCTIMER_TST 0x01CA 447 448 /* Packet arbiter registers */ 449 #define SK_RXPA1_TINIT 0x01D0 450 #define SK_RXPA2_TINIT 0x01D4 451 #define SK_TXPA1_TINIT 0x01D8 452 #define SK_TXPA2_TINIT 0x01DC 453 #define SK_RXPA1_TIMEO 0x01E0 454 #define SK_RXPA2_TIMEO 0x01E4 455 #define SK_TXPA1_TIMEO 0x01E8 456 #define SK_TXPA2_TIMEO 0x01EC 457 #define SK_PKTARB_CTL 0x01F0 458 #define SK_PKTATB_TST 0x01F2 459 460 #define SK_PKTARB_TIMEOUT 0x2000 461 462 #define SK_PKTARBCTL_RESET 0x0001 463 #define SK_PKTARBCTL_UNRESET 0x0002 464 #define SK_PKTARBCTL_RXTO1_OFF 0x0004 465 #define SK_PKTARBCTL_RXTO1_ON 0x0008 466 #define SK_PKTARBCTL_RXTO2_OFF 0x0010 467 #define SK_PKTARBCTL_RXTO2_ON 0x0020 468 #define SK_PKTARBCTL_TXTO1_OFF 0x0040 469 #define SK_PKTARBCTL_TXTO1_ON 0x0080 470 #define SK_PKTARBCTL_TXTO2_OFF 0x0100 471 #define SK_PKTARBCTL_TXTO2_ON 0x0200 472 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 473 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 474 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 475 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 476 477 #define SK_MINIT_XMAC_B2 54 478 #define SK_MINIT_XMAC_C1 63 479 480 #define SK_MACARBCTL_RESET 0x0001 481 #define SK_MACARBCTL_UNRESET 0x0002 482 #define SK_MACARBCTL_FASTOE_OFF 0x0004 483 #define SK_MACARBCRL_FASTOE_ON 0x0008 484 485 #define SK_RCINIT_XMAC_B2 54 486 #define SK_RCINIT_XMAC_C1 0 487 488 #define SK_RECOVERYCTL_RX1_OFF 0x0001 489 #define SK_RECOVERYCTL_RX1_ON 0x0002 490 #define SK_RECOVERYCTL_RX2_OFF 0x0004 491 #define SK_RECOVERYCTL_RX2_ON 0x0008 492 #define SK_RECOVERYCTL_TX1_OFF 0x0010 493 #define SK_RECOVERYCTL_TX1_ON 0x0020 494 #define SK_RECOVERYCTL_TX2_OFF 0x0040 495 #define SK_RECOVERYCTL_TX2_ON 0x0080 496 497 #define SK_RECOVERY_XMAC_B2 \ 498 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 499 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 500 501 #define SK_RECOVERY_XMAC_C1 \ 502 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 503 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 504 505 /* Block 4 -- TX Arbiter MAC 1 */ 506 #define SK_TXAR1_TIMERINIT 0x0200 507 #define SK_TXAR1_TIMERVAL 0x0204 508 #define SK_TXAR1_LIMITINIT 0x0208 509 #define SK_TXAR1_LIMITCNT 0x020C 510 #define SK_TXAR1_COUNTERCTL 0x0210 511 #define SK_TXAR1_COUNTERTST 0x0212 512 #define SK_TXAR1_COUNTERSTS 0x0212 513 514 /* Block 5 -- TX Arbiter MAC 2 */ 515 #define SK_TXAR2_TIMERINIT 0x0280 516 #define SK_TXAR2_TIMERVAL 0x0284 517 #define SK_TXAR2_LIMITINIT 0x0288 518 #define SK_TXAR2_LIMITCNT 0x028C 519 #define SK_TXAR2_COUNTERCTL 0x0290 520 #define SK_TXAR2_COUNTERTST 0x0291 521 #define SK_TXAR2_COUNTERSTS 0x0292 522 523 #define SK_TXARCTL_OFF 0x01 524 #define SK_TXARCTL_ON 0x02 525 #define SK_TXARCTL_RATECTL_OFF 0x04 526 #define SK_TXARCTL_RATECTL_ON 0x08 527 #define SK_TXARCTL_ALLOC_OFF 0x10 528 #define SK_TXARCTL_ALLOC_ON 0x20 529 #define SK_TXARCTL_FSYNC_OFF 0x40 530 #define SK_TXARCTL_FSYNC_ON 0x80 531 532 /* Block 6 -- External registers */ 533 #define SK_EXTREG_BASE 0x300 534 #define SK_EXTREG_END 0x37C 535 536 /* Block 7 -- PCI config registers */ 537 #define SK_PCI_BASE 0x0380 538 #define SK_PCI_END 0x03FC 539 540 /* Compute offset of mirrored PCI register */ 541 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 542 543 /* Block 8 -- RX queue 1 */ 544 #define SK_RXQ1_BUFCNT 0x0400 545 #define SK_RXQ1_BUFCTL 0x0402 546 #define SK_RXQ1_NEXTDESC 0x0404 547 #define SK_RXQ1_RXBUF_LO 0x0408 548 #define SK_RXQ1_RXBUF_HI 0x040C 549 #define SK_RXQ1_RXSTAT 0x0410 550 #define SK_RXQ1_TIMESTAMP 0x0414 551 #define SK_RXQ1_CSUM1 0x0418 552 #define SK_RXQ1_CSUM2 0x041A 553 #define SK_RXQ1_CSUM1_START 0x041C 554 #define SK_RXQ1_CSUM2_START 0x041E 555 #define SK_RXQ1_CURADDR_LO 0x0420 556 #define SK_RXQ1_CURADDR_HI 0x0424 557 #define SK_RXQ1_CURCNT_LO 0x0428 558 #define SK_RXQ1_CURCNT_HI 0x042C 559 #define SK_RXQ1_CURBYTES 0x0430 560 #define SK_RXQ1_BMU_CSR 0x0434 561 #define SK_RXQ1_WATERMARK 0x0438 562 #define SK_RXQ1_FLAG 0x043A 563 #define SK_RXQ1_TEST1 0x043C 564 #define SK_RXQ1_TEST2 0x0440 565 #define SK_RXQ1_TEST3 0x0444 566 567 /* Block 9 -- RX queue 2 */ 568 #define SK_RXQ2_BUFCNT 0x0480 569 #define SK_RXQ2_BUFCTL 0x0482 570 #define SK_RXQ2_NEXTDESC 0x0484 571 #define SK_RXQ2_RXBUF_LO 0x0488 572 #define SK_RXQ2_RXBUF_HI 0x048C 573 #define SK_RXQ2_RXSTAT 0x0490 574 #define SK_RXQ2_TIMESTAMP 0x0494 575 #define SK_RXQ2_CSUM1 0x0498 576 #define SK_RXQ2_CSUM2 0x049A 577 #define SK_RXQ2_CSUM1_START 0x049C 578 #define SK_RXQ2_CSUM2_START 0x049E 579 #define SK_RXQ2_CURADDR_LO 0x04A0 580 #define SK_RXQ2_CURADDR_HI 0x04A4 581 #define SK_RXQ2_CURCNT_LO 0x04A8 582 #define SK_RXQ2_CURCNT_HI 0x04AC 583 #define SK_RXQ2_CURBYTES 0x04B0 584 #define SK_RXQ2_BMU_CSR 0x04B4 585 #define SK_RXQ2_WATERMARK 0x04B8 586 #define SK_RXQ2_FLAG 0x04BA 587 #define SK_RXQ2_TEST1 0x04BC 588 #define SK_RXQ2_TEST2 0x04C0 589 #define SK_RXQ2_TEST3 0x04C4 590 591 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001 592 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002 593 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004 594 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008 595 #define SK_RXBMU_RX_START 0x00000010 596 #define SK_RXBMU_RX_STOP 0x00000020 597 #define SK_RXBMU_POLL_OFF 0x00000040 598 #define SK_RXBMU_POLL_ON 0x00000080 599 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 600 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 601 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400 602 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 603 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000 604 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 605 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 606 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 607 #define SK_RXBMU_PFI_SM_RESET 0x00010000 608 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000 609 #define SK_RXBMU_FIFO_RESET 0x00040000 610 #define SK_RXBMU_FIFO_UNRESET 0x00080000 611 #define SK_RXBMU_DESC_RESET 0x00100000 612 #define SK_RXBMU_DESC_UNRESET 0x00200000 613 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 614 615 #define SK_RXBMU_ONLINE \ 616 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 617 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 618 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 619 SK_RXBMU_DESC_UNRESET) 620 621 #define SK_RXBMU_OFFLINE \ 622 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 623 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 624 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 625 SK_RXBMU_DESC_RESET) 626 627 /* Block 12 -- TX sync queue 1 */ 628 #define SK_TXQS1_BUFCNT 0x0600 629 #define SK_TXQS1_BUFCTL 0x0602 630 #define SK_TXQS1_NEXTDESC 0x0604 631 #define SK_TXQS1_RXBUF_LO 0x0608 632 #define SK_TXQS1_RXBUF_HI 0x060C 633 #define SK_TXQS1_RXSTAT 0x0610 634 #define SK_TXQS1_CSUM_STARTVAL 0x0614 635 #define SK_TXQS1_CSUM_STARTPOS 0x0618 636 #define SK_TXQS1_CSUM_WRITEPOS 0x061A 637 #define SK_TXQS1_CURADDR_LO 0x0620 638 #define SK_TXQS1_CURADDR_HI 0x0624 639 #define SK_TXQS1_CURCNT_LO 0x0628 640 #define SK_TXQS1_CURCNT_HI 0x062C 641 #define SK_TXQS1_CURBYTES 0x0630 642 #define SK_TXQS1_BMU_CSR 0x0634 643 #define SK_TXQS1_WATERMARK 0x0638 644 #define SK_TXQS1_FLAG 0x063A 645 #define SK_TXQS1_TEST1 0x063C 646 #define SK_TXQS1_TEST2 0x0640 647 #define SK_TXQS1_TEST3 0x0644 648 649 /* Block 13 -- TX async queue 1 */ 650 #define SK_TXQA1_BUFCNT 0x0680 651 #define SK_TXQA1_BUFCTL 0x0682 652 #define SK_TXQA1_NEXTDESC 0x0684 653 #define SK_TXQA1_RXBUF_LO 0x0688 654 #define SK_TXQA1_RXBUF_HI 0x068C 655 #define SK_TXQA1_RXSTAT 0x0690 656 #define SK_TXQA1_CSUM_STARTVAL 0x0694 657 #define SK_TXQA1_CSUM_STARTPOS 0x0698 658 #define SK_TXQA1_CSUM_WRITEPOS 0x069A 659 #define SK_TXQA1_CURADDR_LO 0x06A0 660 #define SK_TXQA1_CURADDR_HI 0x06A4 661 #define SK_TXQA1_CURCNT_LO 0x06A8 662 #define SK_TXQA1_CURCNT_HI 0x06AC 663 #define SK_TXQA1_CURBYTES 0x06B0 664 #define SK_TXQA1_BMU_CSR 0x06B4 665 #define SK_TXQA1_WATERMARK 0x06B8 666 #define SK_TXQA1_FLAG 0x06BA 667 #define SK_TXQA1_TEST1 0x06BC 668 #define SK_TXQA1_TEST2 0x06C0 669 #define SK_TXQA1_TEST3 0x06C4 670 671 /* Block 14 -- TX sync queue 2 */ 672 #define SK_TXQS2_BUFCNT 0x0700 673 #define SK_TXQS2_BUFCTL 0x0702 674 #define SK_TXQS2_NEXTDESC 0x0704 675 #define SK_TXQS2_RXBUF_LO 0x0708 676 #define SK_TXQS2_RXBUF_HI 0x070C 677 #define SK_TXQS2_RXSTAT 0x0710 678 #define SK_TXQS2_CSUM_STARTVAL 0x0714 679 #define SK_TXQS2_CSUM_STARTPOS 0x0718 680 #define SK_TXQS2_CSUM_WRITEPOS 0x071A 681 #define SK_TXQS2_CURADDR_LO 0x0720 682 #define SK_TXQS2_CURADDR_HI 0x0724 683 #define SK_TXQS2_CURCNT_LO 0x0728 684 #define SK_TXQS2_CURCNT_HI 0x072C 685 #define SK_TXQS2_CURBYTES 0x0730 686 #define SK_TXQS2_BMU_CSR 0x0734 687 #define SK_TXQS2_WATERMARK 0x0738 688 #define SK_TXQS2_FLAG 0x073A 689 #define SK_TXQS2_TEST1 0x073C 690 #define SK_TXQS2_TEST2 0x0740 691 #define SK_TXQS2_TEST3 0x0744 692 693 /* Block 15 -- TX async queue 2 */ 694 #define SK_TXQA2_BUFCNT 0x0780 695 #define SK_TXQA2_BUFCTL 0x0782 696 #define SK_TXQA2_NEXTDESC 0x0784 697 #define SK_TXQA2_RXBUF_LO 0x0788 698 #define SK_TXQA2_RXBUF_HI 0x078C 699 #define SK_TXQA2_RXSTAT 0x0790 700 #define SK_TXQA2_CSUM_STARTVAL 0x0794 701 #define SK_TXQA2_CSUM_STARTPOS 0x0798 702 #define SK_TXQA2_CSUM_WRITEPOS 0x079A 703 #define SK_TXQA2_CURADDR_LO 0x07A0 704 #define SK_TXQA2_CURADDR_HI 0x07A4 705 #define SK_TXQA2_CURCNT_LO 0x07A8 706 #define SK_TXQA2_CURCNT_HI 0x07AC 707 #define SK_TXQA2_CURBYTES 0x07B0 708 #define SK_TXQA2_BMU_CSR 0x07B4 709 #define SK_TXQA2_WATERMARK 0x07B8 710 #define SK_TXQA2_FLAG 0x07BA 711 #define SK_TXQA2_TEST1 0x07BC 712 #define SK_TXQA2_TEST2 0x07C0 713 #define SK_TXQA2_TEST3 0x07C4 714 715 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001 716 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002 717 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004 718 #define SK_TXBMU_TX_START 0x00000010 719 #define SK_TXBMU_TX_STOP 0x00000020 720 #define SK_TXBMU_POLL_OFF 0x00000040 721 #define SK_TXBMU_POLL_ON 0x00000080 722 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 723 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 724 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400 725 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 726 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000 727 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 728 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 729 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 730 #define SK_TXBMU_PFI_SM_RESET 0x00010000 731 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000 732 #define SK_TXBMU_FIFO_RESET 0x00040000 733 #define SK_TXBMU_FIFO_UNRESET 0x00080000 734 #define SK_TXBMU_DESC_RESET 0x00100000 735 #define SK_TXBMU_DESC_UNRESET 0x00200000 736 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 737 738 #define SK_TXBMU_ONLINE \ 739 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 740 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 741 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 742 SK_TXBMU_DESC_UNRESET) 743 744 #define SK_TXBMU_OFFLINE \ 745 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 746 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 747 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 748 SK_TXBMU_DESC_RESET) 749 750 /* Block 16 -- Receive RAMbuffer 1 */ 751 #define SK_RXRB1_START 0x0800 752 #define SK_RXRB1_END 0x0804 753 #define SK_RXRB1_WR_PTR 0x0808 754 #define SK_RXRB1_RD_PTR 0x080C 755 #define SK_RXRB1_UTHR_PAUSE 0x0810 756 #define SK_RXRB1_LTHR_PAUSE 0x0814 757 #define SK_RXRB1_UTHR_HIPRIO 0x0818 758 #define SK_RXRB1_UTHR_LOPRIO 0x081C 759 #define SK_RXRB1_PKTCNT 0x0820 760 #define SK_RXRB1_LVL 0x0824 761 #define SK_RXRB1_CTLTST 0x0828 762 763 /* Block 17 -- Receive RAMbuffer 2 */ 764 #define SK_RXRB2_START 0x0880 765 #define SK_RXRB2_END 0x0884 766 #define SK_RXRB2_WR_PTR 0x0888 767 #define SK_RXRB2_RD_PTR 0x088C 768 #define SK_RXRB2_UTHR_PAUSE 0x0890 769 #define SK_RXRB2_LTHR_PAUSE 0x0894 770 #define SK_RXRB2_UTHR_HIPRIO 0x0898 771 #define SK_RXRB2_UTHR_LOPRIO 0x089C 772 #define SK_RXRB2_PKTCNT 0x08A0 773 #define SK_RXRB2_LVL 0x08A4 774 #define SK_RXRB2_CTLTST 0x08A8 775 776 /* Block 20 -- Sync. Transmit RAMbuffer 1 */ 777 #define SK_TXRBS1_START 0x0A00 778 #define SK_TXRBS1_END 0x0A04 779 #define SK_TXRBS1_WR_PTR 0x0A08 780 #define SK_TXRBS1_RD_PTR 0x0A0C 781 #define SK_TXRBS1_PKTCNT 0x0A20 782 #define SK_TXRBS1_LVL 0x0A24 783 #define SK_TXRBS1_CTLTST 0x0A28 784 785 /* Block 21 -- Async. Transmit RAMbuffer 1 */ 786 #define SK_TXRBA1_START 0x0A80 787 #define SK_TXRBA1_END 0x0A84 788 #define SK_TXRBA1_WR_PTR 0x0A88 789 #define SK_TXRBA1_RD_PTR 0x0A8C 790 #define SK_TXRBA1_PKTCNT 0x0AA0 791 #define SK_TXRBA1_LVL 0x0AA4 792 #define SK_TXRBA1_CTLTST 0x0AA8 793 794 /* Block 22 -- Sync. Transmit RAMbuffer 2 */ 795 #define SK_TXRBS2_START 0x0B00 796 #define SK_TXRBS2_END 0x0B04 797 #define SK_TXRBS2_WR_PTR 0x0B08 798 #define SK_TXRBS2_RD_PTR 0x0B0C 799 #define SK_TXRBS2_PKTCNT 0x0B20 800 #define SK_TXRBS2_LVL 0x0B24 801 #define SK_TXRBS2_CTLTST 0x0B28 802 803 /* Block 23 -- Async. Transmit RAMbuffer 2 */ 804 #define SK_TXRBA2_START 0x0B80 805 #define SK_TXRBA2_END 0x0B84 806 #define SK_TXRBA2_WR_PTR 0x0B88 807 #define SK_TXRBA2_RD_PTR 0x0B8C 808 #define SK_TXRBA2_PKTCNT 0x0BA0 809 #define SK_TXRBA2_LVL 0x0BA4 810 #define SK_TXRBA2_CTLTST 0x0BA8 811 812 #define SK_RBCTL_RESET 0x00000001 813 #define SK_RBCTL_UNRESET 0x00000002 814 #define SK_RBCTL_OFF 0x00000004 815 #define SK_RBCTL_ON 0x00000008 816 #define SK_RBCTL_STORENFWD_OFF 0x00000010 817 #define SK_RBCTL_STORENFWD_ON 0x00000020 818 819 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 820 #define SK_RXF1_END 0x0C00 821 #define SK_RXF1_WPTR 0x0C04 822 #define SK_RXF1_RPTR 0x0C0C 823 #define SK_RXF1_PKTCNT 0x0C10 824 #define SK_RXF1_LVL 0x0C14 825 #define SK_RXF1_MACCTL 0x0C18 826 #define SK_RXF1_CTL 0x0C1C 827 #define SK_RXLED1_CNTINIT 0x0C20 828 #define SK_RXLED1_COUNTER 0x0C24 829 #define SK_RXLED1_CTL 0x0C28 830 #define SK_RXLED1_TST 0x0C29 831 #define SK_LINK_SYNC1_CINIT 0x0C30 832 #define SK_LINK_SYNC1_COUNTER 0x0C34 833 #define SK_LINK_SYNC1_CTL 0x0C38 834 #define SK_LINK_SYNC1_TST 0x0C39 835 #define SK_LINKLED1_CTL 0x0C3C 836 837 #define SK_FIFO_END 0x3F 838 839 /* Receive MAC FIFO 1 (Yukon Only) */ 840 #define SK_RXMF1_END 0x0C40 841 #define SK_RXMF1_THRESHOLD 0x0C44 842 #define SK_RXMF1_CTRL_TEST 0x0C48 843 #define SK_RXMF1_WRITE_PTR 0x0C60 844 #define SK_RXMF1_WRITE_LEVEL 0x0C68 845 #define SK_RXMF1_READ_PTR 0x0C70 846 #define SK_RXMF1_READ_LEVEL 0x0C78 847 848 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 849 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 850 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 851 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 852 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 853 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 854 #define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */ 855 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 856 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 857 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 858 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 859 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 860 861 862 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 863 #define SK_RXF2_END 0x0C80 864 #define SK_RXF2_WPTR 0x0C84 865 #define SK_RXF2_RPTR 0x0C8C 866 #define SK_RXF2_PKTCNT 0x0C90 867 #define SK_RXF2_LVL 0x0C94 868 #define SK_RXF2_MACCTL 0x0C98 869 #define SK_RXF2_CTL 0x0C9C 870 #define SK_RXLED2_CNTINIT 0x0CA0 871 #define SK_RXLED2_COUNTER 0x0CA4 872 #define SK_RXLED2_CTL 0x0CA8 873 #define SK_RXLED2_TST 0x0CA9 874 #define SK_LINK_SYNC2_CINIT 0x0CB0 875 #define SK_LINK_SYNC2_COUNTER 0x0CB4 876 #define SK_LINK_SYNC2_CTL 0x0CB8 877 #define SK_LINK_SYNC2_TST 0x0CB9 878 #define SK_LINKLED2_CTL 0x0CBC 879 880 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 881 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 882 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004 883 #define SK_RXMACCTL_RSTAMP_ON 0x00000008 884 #define SK_RXMACCTL_FLUSH_OFF 0x00000010 885 #define SK_RXMACCTL_FLUSH_ON 0x00000020 886 #define SK_RXMACCTL_PAUSE_OFF 0x00000040 887 #define SK_RXMACCTL_PAUSE_ON 0x00000080 888 #define SK_RXMACCTL_AFULL_OFF 0x00000100 889 #define SK_RXMACCTL_AFULL_ON 0x00000200 890 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 891 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 892 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 893 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 894 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000 895 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 896 897 #define SK_RXLEDCTL_ENABLE 0x0001 898 #define SK_RXLEDCTL_COUNTER_STOP 0x0002 899 #define SK_RXLEDCTL_COUNTER_START 0x0004 900 901 #define SK_LINKLED_OFF 0x0001 902 #define SK_LINKLED_ON 0x0002 903 #define SK_LINKLED_LINKSYNC_OFF 0x0004 904 #define SK_LINKLED_LINKSYNC_ON 0x0008 905 #define SK_LINKLED_BLINK_OFF 0x0010 906 #define SK_LINKLED_BLINK_ON 0x0020 907 908 /* Block 26 -- TX MAC FIFO 1 regisrers */ 909 #define SK_TXF1_END 0x0D00 910 #define SK_TXF1_WPTR 0x0D04 911 #define SK_TXF1_RPTR 0x0D0C 912 #define SK_TXF1_PKTCNT 0x0D10 913 #define SK_TXF1_LVL 0x0D14 914 #define SK_TXF1_MACCTL 0x0D18 915 #define SK_TXF1_CTL 0x0D1C 916 #define SK_TXLED1_CNTINIT 0x0D20 917 #define SK_TXLED1_COUNTER 0x0D24 918 #define SK_TXLED1_CTL 0x0D28 919 #define SK_TXLED1_TST 0x0D29 920 921 /* Receive MAC FIFO 1 (Yukon Only) */ 922 #define SK_TXMF1_END 0x0D40 923 #define SK_TXMF1_THRESHOLD 0x0D44 924 #define SK_TXMF1_CTRL_TEST 0x0D48 925 #define SK_TXMF1_WRITE_PTR 0x0D60 926 #define SK_TXMF1_WRITE_SHADOW 0x0D64 927 #define SK_TXMF1_WRITE_LEVEL 0x0D68 928 #define SK_TXMF1_READ_PTR 0x0D70 929 #define SK_TXMF1_RESTART_PTR 0x0D74 930 #define SK_TXMF1_READ_LEVEL 0x0D78 931 932 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 933 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 934 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 935 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 936 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 937 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 938 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 939 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 940 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 941 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 942 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 943 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 944 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 945 946 /* Block 27 -- TX MAC FIFO 2 regisrers */ 947 #define SK_TXF2_END 0x0D80 948 #define SK_TXF2_WPTR 0x0D84 949 #define SK_TXF2_RPTR 0x0D8C 950 #define SK_TXF2_PKTCNT 0x0D90 951 #define SK_TXF2_LVL 0x0D94 952 #define SK_TXF2_MACCTL 0x0D98 953 #define SK_TXF2_CTL 0x0D9C 954 #define SK_TXLED2_CNTINIT 0x0DA0 955 #define SK_TXLED2_COUNTER 0x0DA4 956 #define SK_TXLED2_CTL 0x0DA8 957 #define SK_TXLED2_TST 0x0DA9 958 959 #define SK_TXMACCTL_XMAC_RESET 0x00000001 960 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002 961 #define SK_TXMACCTL_LOOP_OFF 0x00000004 962 #define SK_TXMACCTL_LOOP_ON 0x00000008 963 #define SK_TXMACCTL_FLUSH_OFF 0x00000010 964 #define SK_TXMACCTL_FLUSH_ON 0x00000020 965 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 966 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 967 #define SK_TXMACCTL_AFULL_OFF 0x00000100 968 #define SK_TXMACCTL_AFULL_ON 0x00000200 969 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 970 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 971 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 972 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 973 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 974 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 975 976 #define SK_TXLEDCTL_ENABLE 0x0001 977 #define SK_TXLEDCTL_COUNTER_STOP 0x0002 978 #define SK_TXLEDCTL_COUNTER_START 0x0004 979 980 #define SK_FIFO_RESET 0x00000001 981 #define SK_FIFO_UNRESET 0x00000002 982 #define SK_FIFO_OFF 0x00000004 983 #define SK_FIFO_ON 0x00000008 984 985 /* Block 28 -- Descriptor Poll Timer */ 986 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 987 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 988 989 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 990 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 991 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 992 993 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 994 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 995 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 996 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 997 998 /* Block 29 -- reserved */ 999 1000 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1001 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1002 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1003 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1004 #define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */ 1005 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1006 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1007 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1008 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1009 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1010 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1011 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1012 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1013 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1014 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1015 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1016 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1017 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1018 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1019 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1020 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1021 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1022 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1023 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1024 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1025 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1026 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1027 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1028 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1029 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1030 1031 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1032 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1033 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1034 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1035 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1036 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1037 1038 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1039 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1040 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1041 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1042 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1043 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1044 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1045 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1046 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1047 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1048 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1049 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1050 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1051 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1052 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1053 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1054 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1055 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1056 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1057 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1058 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1059 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1060 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1061 1062 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1063 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1064 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1065 SK_GPHY_HWCFG_M_2 ) 1066 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1067 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1068 1069 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1070 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1071 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1072 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1073 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1074 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1075 1076 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1077 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1078 1079 /* Block 31 -- reserved */ 1080 1081 /* Block 32-33 -- Pattern Ram */ 1082 #define SK_WOL_PRAM 0x1000 1083 1084 /* Block 0x22 - 0x3f -- reserved */ 1085 1086 /* Block 0x40 to 0x4F -- XMAC 1 registers */ 1087 #define SK_XMAC1_BASE 0x2000 1088 1089 /* Block 0x50 to 0x5F -- MARV 1 registers */ 1090 #define SK_MARV1_BASE 0x2800 1091 1092 /* Block 0x60 to 0x6F -- XMAC 2 registers */ 1093 #define SK_XMAC2_BASE 0x3000 1094 1095 /* Block 0x70 to 0x7F -- MARV 2 registers */ 1096 #define SK_MARV2_BASE 0x3800 1097 1098 /* Compute relative offset of an XMAC register in the XMAC window(s). */ 1099 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1100 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1101 1102 #if 0 1103 #define SK_XM_READ_4(sc, reg) \ 1104 ((sk_win_read_2(sc->sk_softc, \ 1105 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1106 ((sk_win_read_2(sc->sk_softc, \ 1107 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1108 1109 #define SK_XM_WRITE_4(sc, reg, val) \ 1110 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1111 ((val) & 0xFFFF)); \ 1112 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1113 ((val) >> 16) & 0xFFFF) 1114 #else 1115 #define SK_XM_READ_4(sc, reg) \ 1116 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1117 1118 #define SK_XM_WRITE_4(sc, reg, val) \ 1119 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1120 #endif 1121 1122 #define SK_XM_READ_2(sc, reg) \ 1123 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1124 1125 #define SK_XM_WRITE_2(sc, reg, val) \ 1126 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1127 1128 #define SK_XM_SETBIT_4(sc, reg, x) \ 1129 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1130 1131 #define SK_XM_CLRBIT_4(sc, reg, x) \ 1132 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1133 1134 #define SK_XM_SETBIT_2(sc, reg, x) \ 1135 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1136 1137 #define SK_XM_CLRBIT_2(sc, reg, x) \ 1138 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1139 1140 /* Compute relative offset of an MARV register in the MARV window(s). */ 1141 #define SK_YU_REG(sc, reg) \ 1142 ((reg) + SK_MARV1_BASE + \ 1143 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1144 1145 #define SK_YU_READ_4(sc, reg) \ 1146 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1147 1148 #define SK_YU_READ_2(sc, reg) \ 1149 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1150 1151 #define SK_YU_WRITE_4(sc, reg, val) \ 1152 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1153 1154 #define SK_YU_WRITE_2(sc, reg, val) \ 1155 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1156 1157 #define SK_YU_SETBIT_4(sc, reg, x) \ 1158 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1159 1160 #define SK_YU_CLRBIT_4(sc, reg, x) \ 1161 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1162 1163 #define SK_YU_SETBIT_2(sc, reg, x) \ 1164 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1165 1166 #define SK_YU_CLRBIT_2(sc, reg, x) \ 1167 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1168 1169 /* 1170 * The default FIFO threshold on the XMAC II is 4 bytes. On 1171 * dual port NICs, this often leads to transmit underruns, so we 1172 * bump the threshold a little. 1173 */ 1174 #define SK_XM_TX_FIFOTHRESH 512 1175 1176 #define SK_PCI_VENDOR_ID 0x0000 1177 #define SK_PCI_DEVICE_ID 0x0002 1178 #define SK_PCI_COMMAND 0x0004 1179 #define SK_PCI_STATUS 0x0006 1180 #define SK_PCI_REVID 0x0008 1181 #define SK_PCI_CLASSCODE 0x0009 1182 #define SK_PCI_CACHELEN 0x000C 1183 #define SK_PCI_LATENCY_TIMER 0x000D 1184 #define SK_PCI_HEADER_TYPE 0x000E 1185 #define SK_PCI_LOMEM 0x0010 1186 #define SK_PCI_LOIO 0x0014 1187 #define SK_PCI_SUBVEN_ID 0x002C 1188 #define SK_PCI_SYBSYS_ID 0x002E 1189 #define SK_PCI_BIOSROM 0x0030 1190 #define SK_PCI_INTLINE 0x003C 1191 #define SK_PCI_INTPIN 0x003D 1192 #define SK_PCI_MINGNT 0x003E 1193 #define SK_PCI_MINLAT 0x003F 1194 1195 /* device specific PCI registers */ 1196 #define SK_PCI_OURREG1 0x0040 1197 #define SK_PCI_OURREG2 0x0044 1198 #define SK_PCI_CAPID 0x0048 /* 8 bits */ 1199 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1200 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1201 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1202 #define SK_PCI_PME_EVENT 0x004F 1203 #define SK_PCI_VPD_CAPID 0x0050 1204 #define SK_PCI_VPD_NEXTPTR 0x0051 1205 #define SK_PCI_VPD_ADDR 0x0052 1206 #define SK_PCI_VPD_DATA 0x0054 1207 1208 #define SK_PSTATE_MASK 0x0003 1209 #define SK_PSTATE_D0 0x0000 1210 #define SK_PSTATE_D1 0x0001 1211 #define SK_PSTATE_D2 0x0002 1212 #define SK_PSTATE_D3 0x0003 1213 #define SK_PME_EN 0x0010 1214 #define SK_PME_STATUS 0x8000 1215 1216 /* 1217 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1218 * read is complete. Set to 1 to initiate a write, will become 0 1219 * when write is finished. 1220 */ 1221 #define SK_VPD_FLAG 0x8000 1222 1223 /* VPD structures */ 1224 struct vpd_res { 1225 u_int8_t vr_id; 1226 u_int8_t vr_len; 1227 u_int8_t vr_pad; 1228 }; 1229 1230 struct vpd_key { 1231 char vk_key[2]; 1232 u_int8_t vk_len; 1233 }; 1234 1235 #define VPD_RES_ID 0x82 /* ID string */ 1236 #define VPD_RES_READ 0x90 /* start of read only area */ 1237 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 1238 #define VPD_RES_END 0x78 /* end tag */ 1239 1240 #define CSR_WRITE_4(sc, reg, val) \ 1241 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1242 #define CSR_WRITE_2(sc, reg, val) \ 1243 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1244 #define CSR_WRITE_1(sc, reg, val) \ 1245 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1246 1247 #define CSR_READ_4(sc, reg) \ 1248 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1249 #define CSR_READ_2(sc, reg) \ 1250 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1251 #define CSR_READ_1(sc, reg) \ 1252 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1253 1254 struct sk_type { 1255 u_int16_t sk_vid; 1256 u_int16_t sk_did; 1257 char *sk_name; 1258 }; 1259 1260 /* RX queue descriptor data structure */ 1261 struct sk_rx_desc { 1262 u_int32_t sk_ctl; 1263 u_int32_t sk_next; 1264 u_int32_t sk_data_lo; 1265 u_int32_t sk_data_hi; 1266 u_int32_t sk_xmac_rxstat; 1267 u_int32_t sk_timestamp; 1268 u_int16_t sk_csum2; 1269 u_int16_t sk_csum1; 1270 u_int16_t sk_csum2_start; 1271 u_int16_t sk_csum1_start; 1272 }; 1273 1274 #define SK_OPCODE_DEFAULT 0x00550000 1275 #define SK_OPCODE_CSUM 0x00560000 1276 1277 #define SK_RXCTL_LEN 0x0000FFFF 1278 #define SK_RXCTL_OPCODE 0x00FF0000 1279 #define SK_RXCTL_TSTAMP_VALID 0x01000000 1280 #define SK_RXCTL_STATUS_VALID 0x02000000 1281 #define SK_RXCTL_DEV0 0x04000000 1282 #define SK_RXCTL_EOF_INTR 0x08000000 1283 #define SK_RXCTL_EOB_INTR 0x10000000 1284 #define SK_RXCTL_LASTFRAG 0x20000000 1285 #define SK_RXCTL_FIRSTFRAG 0x40000000 1286 #define SK_RXCTL_OWN 0x80000000 1287 1288 #define SK_RXSTAT \ 1289 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1290 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1291 1292 struct sk_tx_desc { 1293 u_int32_t sk_ctl; 1294 u_int32_t sk_next; 1295 u_int32_t sk_data_lo; 1296 u_int32_t sk_data_hi; 1297 u_int32_t sk_xmac_txstat; 1298 u_int16_t sk_rsvd0; 1299 u_int16_t sk_csum_startval; 1300 u_int16_t sk_csum_startpos; 1301 u_int16_t sk_csum_writepos; 1302 u_int32_t sk_rsvd1; 1303 }; 1304 1305 #define SK_TXCTL_LEN 0x0000FFFF 1306 #define SK_TXCTL_OPCODE 0x00FF0000 1307 #define SK_TXCTL_SW 0x01000000 1308 #define SK_TXCTL_NOCRC 0x02000000 1309 #define SK_TXCTL_STORENFWD 0x04000000 1310 #define SK_TXCTL_EOF_INTR 0x08000000 1311 #define SK_TXCTL_EOB_INTR 0x10000000 1312 #define SK_TXCTL_LASTFRAG 0x20000000 1313 #define SK_TXCTL_FIRSTFRAG 0x40000000 1314 #define SK_TXCTL_OWN 0x80000000 1315 1316 #define SK_TXSTAT \ 1317 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1318 1319 #define SK_RXBYTES(x) (x) & 0x0000FFFF; 1320 #define SK_TXBYTES SK_RXBYTES 1321 1322 #define SK_TX_RING_CNT 512 1323 #define SK_RX_RING_CNT 256 1324 1325 /* 1326 * Jumbo buffer stuff. Note that we must allocate more jumbo 1327 * buffers than there are descriptors in the receive ring. This 1328 * is because we don't know how long it will take for a packet 1329 * to be released after we hand it off to the upper protocol 1330 * layers. To be safe, we allocate 1.5 times the number of 1331 * receive descriptors. 1332 */ 1333 #define SK_JSLOTS 384 1334 1335 #define SK_JRAWLEN (ETHER_MAX_LEN_JUMBO + ETHER_ALIGN) 1336 #define SK_JLEN SK_JRAWLEN 1337 #define SK_MCLBYTES SK_JLEN 1338 #define SK_JPAGESZ PAGE_SIZE 1339 #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1340 #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1341 1342 struct sk_jpool_entry { 1343 int slot; 1344 LIST_ENTRY(sk_jpool_entry) jpool_entries; 1345 }; 1346 1347 struct sk_chain { 1348 void *sk_desc; 1349 struct mbuf *sk_mbuf; 1350 struct sk_chain *sk_next; 1351 }; 1352 1353 /* 1354 * Number of DMA segments in a TxCB. Note that this is carefully 1355 * chosen to make the total struct size an even power of two. It's 1356 * critical that no TxCB be split across a page boundry since 1357 * no attempt is made to allocate physically contiguous memory. 1358 * 1359 */ 1360 #define SK_NTXSEG 30 1361 1362 struct sk_txmap_entry { 1363 bus_dmamap_t dmamap; 1364 SIMPLEQ_ENTRY(sk_txmap_entry) link; 1365 }; 1366 1367 struct sk_chain_data { 1368 struct sk_chain sk_tx_chain[SK_TX_RING_CNT]; 1369 struct sk_chain sk_rx_chain[SK_RX_RING_CNT]; 1370 struct sk_txmap_entry *sk_tx_map[SK_TX_RING_CNT]; 1371 bus_dmamap_t sk_rx_map[SK_RX_RING_CNT]; 1372 bus_dmamap_t sk_rx_jumbo_map; 1373 int sk_tx_prod; 1374 int sk_tx_cons; 1375 int sk_tx_cnt; 1376 int sk_rx_prod; 1377 int sk_rx_cons; 1378 int sk_rx_cnt; 1379 /* Stick the jumbo mem management stuff here too. */ 1380 caddr_t sk_jslots[SK_JSLOTS]; 1381 void *sk_jumbo_buf; 1382 1383 }; 1384 1385 struct sk_ring_data { 1386 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT]; 1387 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT]; 1388 }; 1389 1390 #define SK_TX_RING_ADDR(sc, i) \ 1391 ((sc)->sk_ring_map->dm_segs[0].ds_addr + \ 1392 offsetof(struct sk_ring_data, sk_tx_ring[(i)])) 1393 1394 #define SK_RX_RING_ADDR(sc, i) \ 1395 ((sc)->sk_ring_map->dm_segs[0].ds_addr + \ 1396 offsetof(struct sk_ring_data, sk_rx_ring[(i)])) 1397 1398 struct sk_bcom_hack { 1399 int reg; 1400 int val; 1401 }; 1402 1403 #define SK_INC(x, y) (x) = (x + 1) % y 1404 1405 /* Forward decl. */ 1406 struct sk_if_softc; 1407 1408 /* Softc for the GEnesis controller. */ 1409 struct sk_softc { 1410 struct device sk_dev; /* generic device */ 1411 bus_space_handle_t sk_bhandle; /* bus space handle */ 1412 bus_space_tag_t sk_btag; /* bus space tag */ 1413 void *sk_intrhand; /* irq handler handle */ 1414 struct resource *sk_irq; /* IRQ resource handle */ 1415 struct resource *sk_res; /* I/O or shared mem handle */ 1416 u_int8_t sk_type; 1417 u_int8_t sk_rev; 1418 char *sk_name; 1419 char *sk_vpd_prodname; 1420 char *sk_vpd_readonly; 1421 u_int32_t sk_rboff; /* RAMbuffer offset */ 1422 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1423 u_int32_t sk_pmd; /* physical media type */ 1424 u_int32_t sk_intrmask; 1425 bus_dma_tag_t sc_dmatag; 1426 struct sk_if_softc *sk_if[2]; 1427 }; 1428 1429 /* Softc for each logical interface */ 1430 struct sk_if_softc { 1431 struct device sk_dev; /* generic device */ 1432 struct arpcom arpcom; /* interface info */ 1433 struct mii_data sk_mii; 1434 u_int8_t sk_port; /* port # on controller */ 1435 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1436 u_int32_t sk_rx_ramstart; 1437 u_int32_t sk_rx_ramend; 1438 u_int32_t sk_tx_ramstart; 1439 u_int32_t sk_tx_ramend; 1440 int sk_phytype; 1441 int sk_phyaddr; 1442 int sk_cnt; 1443 int sk_link; 1444 struct timeout sk_tick_ch; 1445 struct sk_chain_data sk_cdata; 1446 struct sk_ring_data *sk_rdata; 1447 bus_dmamap_t sk_ring_map; 1448 struct sk_softc *sk_softc; /* parent controller */ 1449 int sk_tx_bmu; /* TX BMU register */ 1450 int sk_if_flags; 1451 LIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1452 LIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1453 SIMPLEQ_HEAD(__sk_txmaphead, sk_txmap_entry) sk_txmap_head; 1454 }; 1455 1456 struct skc_attach_args { 1457 u_int16_t skc_port; 1458 }; 1459 1460 #define SK_MAXUNIT 256 1461 #define SK_TIMEOUT 1000 1462