1 /* $OpenBSD: intreg.h,v 1.6 2003/06/02 23:27:55 millert Exp $ */ 2 /* $NetBSD: intreg.h,v 1.6 1997/07/22 20:19:10 pk Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)intreg.h 8.1 (Berkeley) 6/11/93 42 */ 43 44 #include <sparc/sparc/vaddrs.h> 45 46 /* 47 * sun4c interrupt enable register. 48 * 49 * The register is a single byte. C code must use the ienab_bis and 50 * ienab_bic functions found in locore.s. 51 * 52 * The register's physical address is defined here as the register 53 * must be mapped early in the boot process (otherwise NMI handling 54 * will fail). 55 */ 56 #define INT_ENABLE_REG_PHYSADR 0xf5000000 /* phys addr in IOspace */ 57 58 /* 59 * Bits in interrupt enable register. Software interrupt requests must 60 * be cleared in software. This is done in locore.s. The ALLIE bit must 61 * be cleared to clear asynchronous memory error (level 15) interrupts. 62 */ 63 #define IE_L14 0x80 /* enable level 14 (counter 1) interrupts */ 64 #define IE_L10 0x20 /* enable level 10 (counter 0) interrupts */ 65 #define IE_L8 0x10 /* enable level 8 interrupts */ 66 #define IE_L6 0x08 /* request software level 6 interrupt */ 67 #define IE_L4 0x04 /* request software level 4 interrupt */ 68 #define IE_L1 0x02 /* request software level 1 interrupt */ 69 #define IE_ALLIE 0x01 /* enable interrupts */ 70 71 #ifndef _LOCORE 72 void ienab_bis(int bis); /* set given bits */ 73 void ienab_bic(int bic); /* clear given bits */ 74 #endif 75 76 #if defined(SUN4M) 77 #ifdef notyet 78 #define IENAB_SYS ((_MAXNBPG * _MAXNCPU) + 0xc) 79 #define IENAB_P0 0x0008 80 #define IENAB_P1 0x1008 81 #define IENAB_P2 0x2008 82 #define IENAB_P3 0x3008 83 #endif /* notyet */ 84 #endif 85 86 #if defined(SUN4M) 87 /* 88 * Interrupt Control Registers, located in IO space. 89 * (mapped to `locore' for now..) 90 * There are two sets of interrupt registers called `Processor Interrupts' 91 * and `System Interrupts'. The `Processor' set corresponds to the 15 92 * interrupt levels as seen by the CPU. The `System' set corresponds to 93 * a set of devices supported by the implementing chip-set. 94 * 95 * Briefly, the ICR_PI_* are per-processor interrupts; the ICR_SI_* are 96 * system-wide interrupts, and the ICR_ITR selects the processor to get 97 * the system's interrupts. 98 */ 99 #define ICR_PI_PEND (PI_INTR_VA + 0x0) 100 #define ICR_PI_CLR (PI_INTR_VA + 0x4) 101 #define ICR_PI_SET (PI_INTR_VA + 0x8) 102 #define ICR_SI_PEND (SI_INTR_VA) 103 #define ICR_SI_MASK (SI_INTR_VA + 0x4) 104 #define ICR_SI_CLR (SI_INTR_VA + 0x8) 105 #define ICR_SI_SET (SI_INTR_VA + 0xc) 106 #define ICR_ITR (SI_INTR_VA + 0x10) 107 108 /* 109 * Bits in interrupt registers. Software interrupt requests must 110 * be cleared in software. This is done in locore.s. 111 * There are separate registers for reading pending interrupts and 112 * setting/clearing (software) interrupts. 113 */ 114 #define PINTR_SINTRLEV(n) (1 << (16 + (n))) 115 #define PINTR_IC 0x8000 /* Level 15 clear */ 116 117 #define SINTR_MA 0x80000000 /* Mask All interrupts */ 118 #define SINTR_ME 0x40000000 /* Module Error (async) */ 119 #define SINTR_I 0x20000000 /* MSI (MBus-SBus) */ 120 #define SINTR_M 0x10000000 /* ECC Memory controller */ 121 #define SINTR_V 0x08000000 /* VME Async error */ 122 #define SINTR_RSVD2 0x07800000 123 #define SINTR_F 0x00400000 /* Floppy */ 124 #define SINTR_MI 0x00200000 /* Module interrupt */ 125 #define SINTR_VI 0x00100000 /* Video (Supersparc only) */ 126 #define SINTR_T 0x00080000 /* Level 10 counter */ 127 #define SINTR_SC 0x00040000 /* SCSI */ 128 #define SINTR_A 0x00020000 /* Audio/ISDN */ 129 #define SINTR_E 0x00010000 /* Ethernet */ 130 #define SINTR_S 0x00008000 /* Serial port */ 131 #define SINTR_K 0x00004000 /* Keyboard/mouse */ 132 #define SINTR_SBUSMASK 0x00003f80 /* SBus */ 133 #define SINTR_SBUS(n) (1 << (7+(n)-1)) 134 #define SINTR_VMEMASK 0x0000007f /* VME */ 135 #define SINTR_VME(n) (1 << ((n)-1)) 136 #define SINTR_BITS "\177\020" \ 137 "f\0\7VME\0f\7\7SBUS\0b\16K\0b\17S\0b\20E\0" \ 138 "b\21A\0b\22SC\0b\23T\0b\24VI\0b\25MI\0" \ 139 "b\26F\0b\33V\0b\34M\0b\35I\0b\36ME\0b\37MA\0" 140 141 142 #endif 143