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Searched refs:SIMM16 (Results 1 – 4 of 4) sorted by relevance

/mirbsd/src/gnu/usr.bin/binutils/opcodes/
Dm10200-opc.c121 #define SIMM16 (SIMM8+1) macro
125 #define SIMM16N (SIMM16+1)
199 { "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}},
243 { "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
246 { "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}},
271 { "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
Dm10300-opc.c180 #define SIMM16 (SIMM8+1) macro
184 #define PAREN (SIMM16+1)
535 { "mov", 0x2c0000, 0xfc0000, 0, FMT_S2, 0, {SIMM16, DN0}},
768 { "add", 0xfac00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
770 { "add", 0xfad00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, AN0}},
772 { "add", 0xfafe0000, 0xffff0000, 0, FMT_D2, 0, {SIMM16, SP}},
840 { "cmp", 0xfac80000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1160 { "udf00", 0xfb000000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1164 { "udf01", 0xfb100000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1168 { "udf02", 0xfb200000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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Dm32r-opc.c297 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
435 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
447 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
891 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
909 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
927 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
Dm32r-opinst.c92 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
191 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
420 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },