1 /* $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $ */
2
3 /*
4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #ifndef _SDMMCREG_H_
20 #define _SDMMCREG_H_
21
22 /* MMC commands */ /* response type */
23 #define MMC_GO_IDLE_STATE 0 /* R0 */
24 #define MMC_SEND_OP_COND 1 /* R3 */
25 #define MMC_ALL_SEND_CID 2 /* R2 */
26 #define MMC_SET_RELATIVE_ADDR 3 /* R1 */
27 #define MMC_SELECT_CARD 7 /* R1 */
28 #define MMC_SEND_CSD 9 /* R2 */
29 #define MMC_STOP_TRANSMISSION 12 /* R1B */
30 #define MMC_SEND_STATUS 13 /* R1 */
31 #define MMC_SET_BLOCKLEN 16 /* R1 */
32 #define MMC_READ_BLOCK_SINGLE 17 /* R1 */
33 #define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */
34 #define MMC_SET_BLOCK_COUNT 23 /* R1 */
35 #define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */
36 #define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */
37 #define MMC_APP_CMD 55 /* R1 */
38
39 /* SD commands */ /* response type */
40 #define SD_SEND_RELATIVE_ADDR 3 /* R6 */
41 #define SD_SEND_IF_COND 8 /* R7 */
42
43 /* SD application commands */ /* response type */
44 #define SD_APP_SET_BUS_WIDTH 6 /* R1 */
45 #define SD_APP_OP_COND 41 /* R3 */
46
47 /* OCR bits */
48 #define MMC_OCR_MEM_READY (1<<31) /* memory power-up status bit */
49 #define MMC_OCR_3_5V_3_6V (1<<23)
50 #define MMC_OCR_3_4V_3_5V (1<<22)
51 #define MMC_OCR_3_3V_3_4V (1<<21)
52 #define MMC_OCR_3_2V_3_3V (1<<20)
53 #define MMC_OCR_3_1V_3_2V (1<<19)
54 #define MMC_OCR_3_0V_3_1V (1<<18)
55 #define MMC_OCR_2_9V_3_0V (1<<17)
56 #define MMC_OCR_2_8V_2_9V (1<<16)
57 #define MMC_OCR_2_7V_2_8V (1<<15)
58 #define MMC_OCR_2_6V_2_7V (1<<14)
59 #define MMC_OCR_2_5V_2_6V (1<<13)
60 #define MMC_OCR_2_4V_2_5V (1<<12)
61 #define MMC_OCR_2_3V_2_4V (1<<11)
62 #define MMC_OCR_2_2V_2_3V (1<<10)
63 #define MMC_OCR_2_1V_2_2V (1<<9)
64 #define MMC_OCR_2_0V_2_1V (1<<8)
65 #define MMC_OCR_1_9V_2_0V (1<<7)
66 #define MMC_OCR_1_8V_1_9V (1<<6)
67 #define MMC_OCR_1_7V_1_8V (1<<5)
68 #define MMC_OCR_1_6V_1_7V (1<<4)
69
70 #define SD_OCR_SDHC_CAP (1<<30)
71 #define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */
72
73 /* R1 response type bits */
74 #define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */
75 #define MMC_R1_APP_CMD (1<<5) /* app. commands supported */
76
77 /* 48-bit response decoding (32 bits w/o CRC) */
78 #define MMC_R1(resp) ((resp)[0])
79 #define MMC_R3(resp) ((resp)[0])
80 #define SD_R6(resp) ((resp)[0])
81
82 /* RCA argument and response */
83 #define MMC_ARG_RCA(rca) ((rca) << 16)
84 #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16)
85
86 /* bus width argument */
87 #define SD_ARG_BUS_WIDTH_1 0
88 #define SD_ARG_BUS_WIDTH_4 2
89
90 /* MMC R2 response (CSD) */
91 #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
92 #define MMC_CSD_CSDVER_1_0 1
93 #define MMC_CSD_CSDVER_2_0 2
94 #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
95 #define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */
96 #define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */
97 #define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */
98 #define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */
99 #define MMC_CSD_MMCVER_4_0 4 /* MMC 4 */
100 #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
101 #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
102 #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \
103 (MMC_CSD_C_SIZE_MULT((resp))+2))
104 #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
105
106 /* MMC v1 R2 response (CID) */
107 #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24)
108 #define MMC_CID_PNM_V1_CPY(resp, pnm) \
109 do { \
110 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
111 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
112 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
113 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
114 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
115 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
116 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \
117 (pnm)[7] = '\0'; \
118 } while (0)
119 #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8)
120 #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24)
121 #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8)
122
123 /* MMC v2 R2 response (CID) */
124 #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8)
125 #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16)
126 #define MMC_CID_PNM_V2_CPY(resp, pnm) \
127 do { \
128 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
129 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
130 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
131 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
132 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
133 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
134 (pnm)[6] = '\0'; \
135 } while (0)
136 #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32)
137
138 /* SD R2 response (CSD) */
139 #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
140 #define SD_CSD_CSDVER_1_0 0
141 #define SD_CSD_CSDVER_2_0 1
142 #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
143 #define SD_CSD_TAAC_1_5_MSEC 0x26
144 #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
145 #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
146 #define SD_CSD_SPEED_25_MHZ 0x32
147 #define SD_CSD_SPEED_50_MHZ 0x5a
148 #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12)
149 #define SD_CSD_CCC_ALL 0x5f5
150 #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
151 #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1)
152 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
153 #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1)
154 #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1)
155 #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
156 #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \
157 (SD_CSD_C_SIZE_MULT((resp))+2))
158 #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22)
159 #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
160 #define SD_CSD_V2_BL_LEN 0x9 /* 512 */
161 #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3)
162 #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3)
163 #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3)
164 #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3)
165 #define SD_CSD_VDD_RW_CURR_100mA 0x7
166 #define SD_CSD_VDD_RW_CURR_80mA 0x6
167 #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
168 #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1)
169 #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */
170 #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */
171 #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1)
172 #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
173 #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
174 #define SD_CSD_RW_BL_LEN_2G 0xa
175 #define SD_CSD_RW_BL_LEN_1G 0x9
176 #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1)
177 #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1)
178 #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1)
179 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
180 #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1)
181 #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2)
182
183 /* SD R2 response (CID) */
184 #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8)
185 #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16)
186 #define SD_CID_PNM_CPY(resp, pnm) \
187 do { \
188 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
189 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
190 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
191 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
192 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
193 (pnm)[5] = '\0'; \
194 } while (0)
195 #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8)
196 #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32)
197 #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12)
198
199 /* Might be slow, but it should work on big and little endian systems. */
200 #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len))
201 static __inline int
__bitfield(u_int32_t * src,int start,int len)202 __bitfield(u_int32_t *src, int start, int len)
203 {
204 u_int8_t *sp;
205 u_int32_t dst, mask;
206 int shift, bs, bc;
207
208 if (start < 0 || len < 0 || len > 32)
209 return 0;
210
211 dst = 0;
212 mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX;
213 shift = 0;
214
215 while (len > 0) {
216 sp = (u_int8_t *)src + start / 8;
217 bs = start % 8;
218 bc = 8 - bs;
219 if (bc > len)
220 bc = len;
221 dst |= (*sp++ >> bs) << shift;
222 shift += bc;
223 start += bc;
224 len -= bc;
225 }
226
227 dst &= mask;
228 return (int)dst;
229 }
230
231 #endif
232