1 /* $OpenBSD: rtl81x9reg.h,v 1.19 2005/04/15 03:13:03 brad Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.14 1999/10/21 19:42:03 wpaul Exp $ 35 */ 36 37 /* 38 * RealTek 8129/8139 register offsets 39 */ 40 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 41 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 42 #define RL_IDR2 0x0002 43 #define RL_IDR3 0x0003 44 #define RL_IDR4 0x0004 45 #define RL_IDR5 0x0005 46 /* 0006-0007 reserved */ 47 #define RL_MAR0 0x0008 /* Multicast hash table */ 48 #define RL_MAR1 0x0009 49 #define RL_MAR2 0x000A 50 #define RL_MAR3 0x000B 51 #define RL_MAR4 0x000C 52 #define RL_MAR5 0x000D 53 #define RL_MAR6 0x000E 54 #define RL_MAR7 0x000F 55 56 #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 57 #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 58 #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 59 #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 60 61 #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 62 #define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 63 #define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 64 #define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 65 66 #define RL_RXADDR 0x0030 /* RX ring start address */ 67 #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 68 #define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 69 #define RL_COMMAND 0x0037 /* command register */ 70 #define RL_CURRXADDR 0x0038 /* current address of packet read */ 71 #define RL_CURRXBUF 0x003A /* current RX buffer address */ 72 #define RL_IMR 0x003C /* interrupt mask register */ 73 #define RL_ISR 0x003E /* interrupt status register */ 74 #define RL_TXCFG 0x0040 /* transmit config */ 75 #define RL_RXCFG 0x0044 /* receive config */ 76 #define RL_TIMERCNT 0x0048 /* timer count register */ 77 #define RL_MISSEDPKT 0x004C /* missed packet counter */ 78 #define RL_EECMD 0x0050 /* EEPROM command register */ 79 #define RL_CFG0 0x0051 /* config register #0 */ 80 #define RL_CFG1 0x0052 /* config register #1 */ 81 /* 0053-0057 reserved */ 82 #define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 83 /* 0059-005A reserved */ 84 #define RL_MII 0x005A /* 8129 chip only */ 85 #define RL_HALTCLK 0x005B 86 #define RL_MULTIINTR 0x005C /* multiple interrupt */ 87 #define RL_PCIREV 0x005E /* PCI revision value */ 88 /* 005F reserved */ 89 #define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 90 91 /* Direct PHY access registers only available on 8139 */ 92 #define RL_BMCR 0x0062 /* PHY basic mode control */ 93 #define RL_BMSR 0x0064 /* PHY basic mode status */ 94 #define RL_ANAR 0x0066 /* PHY autoneg advert */ 95 #define RL_LPAR 0x0068 /* PHY link partner ability */ 96 #define RL_ANER 0x006A /* PHY autoneg expansion */ 97 98 #define RL_DISCCNT 0x006C /* disconnect counter */ 99 #define RL_FALSECAR 0x006E /* false carrier counter */ 100 #define RL_NWAYTST 0x0070 /* NWAY test register */ 101 #define RL_RX_ER 0x0072 /* RX_ER counter */ 102 #define RL_CSCFG 0x0074 /* CS configuration register */ 103 104 /* 105 * When operating in special C+ mode, some of the registers in an 106 * 8139C+ chip have different definitions. These are also used for 107 * the 8169 gigE chip. 108 */ 109 #define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 110 #define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 111 #define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 112 #define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 113 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte aligned */ 114 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte aligned */ 115 #define RL_CFG2 0x0053 116 #define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 117 #define RL_TXSTART 0x00D9 /* 8 bits */ 118 #define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 119 #define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 120 #define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 121 #define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 122 123 /* 124 * Registers specific to the 8169 gigE chip 125 */ 126 #define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 127 #define RL_PHYAR 0x0060 128 #define RL_TBICSR 0x0064 129 #define RL_TBI_ANAR 0x0068 130 #define RL_TBI_LPAR 0x006A 131 #define RL_GMEDIASTAT 0x006C /* 8 bits */ 132 #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 133 #define RL_GTXSTART 0x0038 /* 16 bits */ 134 /* 135 * TX config register bits 136 */ 137 #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 138 #define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 139 #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 140 #define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 141 #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 142 #define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 143 #define RL_TXCFG_HWREV 0x7CC00000 144 145 #define RL_LOOPTEST_OFF 0x00000000 146 #define RL_LOOPTEST_ON 0x00020000 147 #define RL_LOOPTEST_ON_CPLUS 0x00060000 148 149 #define RL_HWREV_8169 0x00000000 150 #define RL_HWREV_8169S 0x04000000 151 #define RL_HWREV_8169SB 0x10000000 152 #define RL_HWREV_8110S 0x00800000 153 #define RL_HWREV_8139 0x60000000 154 #define RL_HWREV_8139A 0x70000000 155 #define RL_HWREV_8139AG 0x70800000 156 #define RL_HWREV_8139B 0x78000000 157 #define RL_HWREV_8130 0x7C000000 158 #define RL_HWREV_8139C 0x74000000 159 #define RL_HWREV_8139D 0x74400000 160 #define RL_HWREV_8139CPLUS 0x74800000 161 #define RL_HWREV_8101 0x74c00000 162 #define RL_HWREV_8100 0x78800000 163 164 #define RL_TXDMA_16BYTES 0x00000000 165 #define RL_TXDMA_32BYTES 0x00000100 166 #define RL_TXDMA_64BYTES 0x00000200 167 #define RL_TXDMA_128BYTES 0x00000300 168 #define RL_TXDMA_256BYTES 0x00000400 169 #define RL_TXDMA_512BYTES 0x00000500 170 #define RL_TXDMA_1024BYTES 0x00000600 171 #define RL_TXDMA_2048BYTES 0x00000700 172 173 /* 174 * Transmit descriptor status register bits. 175 */ 176 #define RL_TXSTAT_LENMASK 0x00001FFF 177 #define RL_TXSTAT_OWN 0x00002000 178 #define RL_TXSTAT_TX_UNDERRUN 0x00004000 179 #define RL_TXSTAT_TX_OK 0x00008000 180 #define RL_TXSTAT_EARLY_THRESH 0x003F0000 181 #define RL_TXSTAT_COLLCNT 0x0F000000 182 #define RL_TXSTAT_CARR_HBEAT 0x10000000 183 #define RL_TXSTAT_OUTOFWIN 0x20000000 184 #define RL_TXSTAT_TXABRT 0x40000000 185 #define RL_TXSTAT_CARRLOSS 0x80000000 186 187 /* 188 * Interrupt status register bits. 189 */ 190 #define RL_ISR_RX_OK 0x0001 191 #define RL_ISR_RX_ERR 0x0002 192 #define RL_ISR_TX_OK 0x0004 193 #define RL_ISR_TX_ERR 0x0008 194 #define RL_ISR_RX_OVERRUN 0x0010 195 #define RL_ISR_PKT_UNDERRUN 0x0020 196 #define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 197 #define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 198 #define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 199 #define RL_ISR_SWI 0x0100 /* C+ only */ 200 #define RL_ISR_CABLE_LEN_CHGD 0x2000 201 #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 202 #define RL_ISR_TIMEOUT_EXPIRED 0x4000 203 #define RL_ISR_SYSTEM_ERR 0x8000 204 205 #define RL_INTRS \ 206 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 207 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 208 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 209 210 #define RL_INTRS_CPLUS \ 211 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 212 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 213 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 214 215 216 /* 217 * Media status register. (8139 only) 218 */ 219 #define RL_MEDIASTAT_RXPAUSE 0x01 220 #define RL_MEDIASTAT_TXPAUSE 0x02 221 #define RL_MEDIASTAT_LINK 0x04 222 #define RL_MEDIASTAT_SPEED10 0x08 223 #define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 224 #define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 225 226 /* 227 * Receive config register. 228 */ 229 #define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 230 #define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 231 #define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 232 #define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 233 #define RL_RXCFG_RX_RUNT 0x00000010 234 #define RL_RXCFG_RX_ERRPKT 0x00000020 235 #define RL_RXCFG_WRAP 0x00000080 236 #define RL_RXCFG_MAXDMA 0x00000700 237 #define RL_RXCFG_BURSZ 0x00001800 238 #define RL_RXCFG_FIFOTHRESH 0x0000E000 239 #define RL_RXCFG_EARLYTHRESH 0x07000000 240 241 #define RL_RXDMA_16BYTES 0x00000000 242 #define RL_RXDMA_32BYTES 0x00000100 243 #define RL_RXDMA_64BYTES 0x00000200 244 #define RL_RXDMA_128BYTES 0x00000300 245 #define RL_RXDMA_256BYTES 0x00000400 246 #define RL_RXDMA_512BYTES 0x00000500 247 #define RL_RXDMA_1024BYTES 0x00000600 248 #define RL_RXDMA_UNLIMITED 0x00000700 249 250 #define RL_RXBUF_8 0x00000000 251 #define RL_RXBUF_16 0x00000800 252 #define RL_RXBUF_32 0x00001000 253 #define RL_RXBUF_64 0x00001800 254 255 #define RL_RXFIFO_16BYTES 0x00000000 256 #define RL_RXFIFO_32BYTES 0x00002000 257 #define RL_RXFIFO_64BYTES 0x00004000 258 #define RL_RXFIFO_128BYTES 0x00006000 259 #define RL_RXFIFO_256BYTES 0x00008000 260 #define RL_RXFIFO_512BYTES 0x0000A000 261 #define RL_RXFIFO_1024BYTES 0x0000C000 262 #define RL_RXFIFO_NOTHRESH 0x0000E000 263 264 /* 265 * Bits in RX status header (included with RX'ed packet 266 * in ring buffer). 267 */ 268 #define RL_RXSTAT_RXOK 0x00000001 269 #define RL_RXSTAT_ALIGNERR 0x00000002 270 #define RL_RXSTAT_CRCERR 0x00000004 271 #define RL_RXSTAT_GIANT 0x00000008 272 #define RL_RXSTAT_RUNT 0x00000010 273 #define RL_RXSTAT_BADSYM 0x00000020 274 #define RL_RXSTAT_BROAD 0x00002000 275 #define RL_RXSTAT_INDIV 0x00004000 276 #define RL_RXSTAT_MULTI 0x00008000 277 #define RL_RXSTAT_LENMASK 0xFFFF0000 278 279 #define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 280 /* 281 * Command register. 282 */ 283 #define RL_CMD_EMPTY_RXBUF 0x0001 284 #define RL_CMD_TX_ENB 0x0004 285 #define RL_CMD_RX_ENB 0x0008 286 #define RL_CMD_RESET 0x0010 287 288 /* 289 * EEPROM control register 290 */ 291 #define RL_EE_DATAOUT 0x01 /* Data out */ 292 #define RL_EE_DATAIN 0x02 /* Data in */ 293 #define RL_EE_CLK 0x04 /* clock */ 294 #define RL_EE_SEL 0x08 /* chip select */ 295 #define RL_EE_MODE (0x40|0x80) 296 297 #define RL_EEMODE_OFF 0x00 298 #define RL_EEMODE_AUTOLOAD 0x40 299 #define RL_EEMODE_PROGRAM 0x80 300 #define RL_EEMODE_WRITECFG (0x80|0x40) 301 302 /* 9346/9356 EEPROM commands */ 303 #define RL_EECMD_WRITE 0x5 /* 0101b */ 304 #define RL_EECMD_READ 0x6 /* 0110b */ 305 #define RL_EECMD_ERASE 0x7 /* 0111b */ 306 #define RL_EECMD_LEN 4 307 308 #define RL_EEADDR_LEN0 6 /* 9346 */ 309 #define RL_EEADDR_LEN1 8 /* 9356 */ 310 311 #define RL_EECMD_READ_6BIT 0x180 /* XXX */ 312 #define RL_EECMD_READ_8BIT 0x600 /* EECMD_READ above maybe wrong? */ 313 314 #define RL_EE_ID 0x00 315 #define RL_EE_PCI_VID 0x01 316 #define RL_EE_PCI_DID 0x02 317 /* Location of station address inside EEPROM */ 318 #define RL_EE_EADDR 0x07 319 320 /* 321 * MII register (8129 only) 322 */ 323 #define RL_MII_CLK 0x01 324 #define RL_MII_DATAIN 0x02 325 #define RL_MII_DATAOUT 0x04 326 #define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 327 328 /* 329 * Config 0 register 330 */ 331 #define RL_CFG0_ROM0 0x01 332 #define RL_CFG0_ROM1 0x02 333 #define RL_CFG0_ROM2 0x04 334 #define RL_CFG0_PL0 0x08 335 #define RL_CFG0_PL1 0x10 336 #define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 337 #define RL_CFG0_PCS 0x40 338 #define RL_CFG0_SCR 0x80 339 340 /* 341 * Config 1 register 342 */ 343 #define RL_CFG1_PWRDWN 0x01 344 #define RL_CFG1_SLEEP 0x02 345 #define RL_CFG1_IOMAP 0x04 346 #define RL_CFG1_MEMMAP 0x08 347 #define RL_CFG1_RSVD 0x10 348 #define RL_CFG1_DRVLOAD 0x20 349 #define RL_CFG1_LED0 0x40 350 #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 351 #define RL_CFG1_LED1 0x80 352 353 /* 354 * 8139C+ register definitions 355 */ 356 357 /* RL_DUMPSTATS_LO register */ 358 359 #define RL_DUMPSTATS_START 0x00000008 360 361 /* Transmit start register */ 362 363 #define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 364 #define RL_TXSTART_START 0x40 /* start normal queue transmit */ 365 #define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 366 367 /* 368 * Config 2 register, 8139C+/8169/8169S/8110S only 369 */ 370 #define RL_CFG2_BUSFREQ 0x07 371 #define RL_CFG2_BUSWIDTH 0x08 372 #define RL_CFG2_AUXPWRSTS 0x10 373 374 #define RL_BUSFREQ_33MHZ 0x00 375 #define RL_BUSFREQ_66MHZ 0x01 376 377 #define RL_BUSWIDTH_32BITS 0x00 378 #define RL_BUSWIDTH_64BITS 0x08 379 380 /* C+ mode command register */ 381 382 #define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 383 #define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 384 #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 385 #define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 386 #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 387 #define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 388 389 /* C+ early transmit threshold */ 390 391 #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 392 393 /* 394 * Gigabit PHY access register (8169 only) 395 */ 396 397 #define RL_PHYAR_PHYDATA 0x0000FFFF 398 #define RL_PHYAR_PHYREG 0x001F0000 399 #define RL_PHYAR_BUSY 0x80000000 400 401 /* 402 * Gigabit media status (8169 only) 403 */ 404 #define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 405 #define RL_GMEDIASTAT_LINK 0x02 /* link up */ 406 #define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 407 #define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 408 #define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 409 #define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 410 #define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 411 #define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 412 413 /* 414 * The RealTek doesn't use a fragment-based descriptor mechanism. 415 * Instead, there are only four register sets, each or which represents 416 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 417 * packet buffer (32-bit aligned!) and we place the buffer addresses in 418 * the registers so the chip knows where they are. 419 * 420 * We can sort of kludge together the same kind of buffer management 421 * used in previous drivers, but we have to do buffer copies almost all 422 * the time, so it doesn't really buy us much. 423 * 424 * For reception, there's just one large buffer where the chip stores 425 * all received packets. 426 */ 427 428 #define RL_RX_BUF_SZ RL_RXBUF_64 429 #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 430 #define RL_TX_LIST_CNT 4 431 #define RL_MIN_FRAMELEN 60 432 #define RL_TXTHRESH(x) ((x) << 11) 433 #define RL_TX_THRESH_INIT 96 434 #define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 435 #define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 436 #define RL_TX_MAXDMA RL_TXDMA_2048BYTES 437 438 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 439 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 440 441 struct rl_chain_data { 442 u_int16_t cur_rx; 443 caddr_t rl_rx_buf; 444 caddr_t rl_rx_buf_ptr; 445 bus_addr_t rl_rx_buf_pa; 446 447 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 448 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 449 u_int8_t last_tx; 450 u_int8_t cur_tx; 451 }; 452 453 454 /* 455 * The 8139C+ and 8160 gigE chips support descriptor-based TX 456 * and RX. In fact, they even support TCP large send. Descriptors 457 * must be allocated in contiguous blocks that are aligned on a 458 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 459 */ 460 461 /* 462 * RX/TX descriptor definition. When large send mode is enabled, the 463 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 464 * the checksum offload bits are disabled. The structure layout is 465 * the same for RX and TX descriptors 466 */ 467 468 struct rl_desc { 469 u_int32_t rl_cmdstat; 470 u_int32_t rl_vlanctl; 471 u_int32_t rl_bufaddr_lo; 472 u_int32_t rl_bufaddr_hi; 473 }; 474 475 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 476 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 477 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 478 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 479 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 480 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 481 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 482 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 483 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 484 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 485 486 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 487 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 488 489 /* 490 * Error bits are valid only on the last descriptor of a frame 491 * (i.e. RL_TDESC_CMD_EOF == 1) 492 */ 493 494 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 495 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 496 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 497 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 498 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 499 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 500 #define RL_TDESC_STAT_OWN 0x80000000 501 502 /* 503 * RX descriptor cmd/vlan definitions 504 */ 505 506 #define RL_RDESC_CMD_EOR 0x40000000 507 #define RL_RDESC_CMD_OWN 0x80000000 508 #define RL_RDESC_CMD_BUFLEN 0x00001FFF 509 510 #define RL_RDESC_STAT_OWN 0x80000000 511 #define RL_RDESC_STAT_EOR 0x40000000 512 #define RL_RDESC_STAT_SOF 0x20000000 513 #define RL_RDESC_STAT_EOF 0x10000000 514 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 515 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 516 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 517 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 518 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 519 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 520 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 521 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 522 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 523 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 524 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 525 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 526 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 527 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 528 #define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 529 #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 530 531 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 532 (rl_vlandata valid)*/ 533 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 534 535 #define RL_PROTOID_NONIP 0x00000000 536 #define RL_PROTOID_TCPIP 0x00010000 537 #define RL_PROTOID_UDPIP 0x00020000 538 #define RL_PROTOID_IP 0x00030000 539 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 540 RL_PROTOID_TCPIP) 541 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 542 RL_PROTOID_UDPIP) 543 544 /* 545 * Statistics counter structure (8139C+ and 8169 only) 546 */ 547 struct rl_stats { 548 u_int32_t rl_tx_pkts_lo; 549 u_int32_t rl_tx_pkts_hi; 550 u_int32_t rl_tx_errs_lo; 551 u_int32_t rl_tx_errs_hi; 552 u_int32_t rl_tx_errs; 553 u_int16_t rl_missed_pkts; 554 u_int16_t rl_rx_framealign_errs; 555 u_int32_t rl_tx_onecoll; 556 u_int32_t rl_tx_multicolls; 557 u_int32_t rl_rx_ucasts_hi; 558 u_int32_t rl_rx_ucasts_lo; 559 u_int32_t rl_rx_bcasts_lo; 560 u_int32_t rl_rx_bcasts_hi; 561 u_int32_t rl_rx_mcasts; 562 u_int16_t rl_tx_aborts; 563 u_int16_t rl_rx_underruns; 564 }; 565 566 #define RL_RX_DESC_CNT 64 567 #define RL_TX_DESC_CNT 64 568 #define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 569 #define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 570 #define RL_RING_ALIGN 256 571 #define RL_IFQ_MAXLEN 512 572 #define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 573 #define RL_OWN(x) (letoh32((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 574 #define RL_RXBYTES(x) (letoh32((x)->rl_cmdstat) & sc->rl_rxlenmask) 575 #define RL_PKTSZ(x) ((x)/* >> 3*/) 576 577 #define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 578 #define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 579 580 /* see comment in dev/ic/re.c */ 581 #define RL_JUMBO_FRAMELEN 7440 582 #define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 583 584 #define MAX_NUM_MULTICAST_ADDRESSES 128 585 586 #define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 587 #define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 588 #define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 589 #define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 590 #define RL_CUR_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 591 #define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 592 #define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 593 #define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 594 #define RL_LAST_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 595 596 struct rl_type { 597 u_int16_t rl_vid; 598 u_int16_t rl_did; 599 }; 600 601 struct rl_mii_frame { 602 u_int8_t mii_stdelim; 603 u_int8_t mii_opcode; 604 u_int8_t mii_phyaddr; 605 u_int8_t mii_regaddr; 606 u_int8_t mii_turnaround; 607 u_int16_t mii_data; 608 }; 609 610 /* 611 * MII constants 612 */ 613 #define RL_MII_STARTDELIM 0x01 614 #define RL_MII_READOP 0x02 615 #define RL_MII_WRITEOP 0x01 616 #define RL_MII_TURNAROUND 0x02 617 618 #define RL_UNKNOWN 0 619 #define RL_8129 1 620 #define RL_8139 2 621 #define RL_8139CPLUS 3 622 #define RL_8169 4 623 624 #define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 625 (x)->rl_type == RL_8169) 626 627 struct rl_list_data { 628 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 629 struct mbuf *rl_rx_mbuf[RL_RX_DESC_CNT]; 630 int rl_tx_prodidx; 631 int rl_rx_prodidx; 632 int rl_tx_considx; 633 int rl_tx_free; 634 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 635 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 636 bus_dmamap_t rl_rx_list_map; 637 struct rl_desc *rl_rx_list; 638 bus_dma_segment_t rl_rx_listseg; 639 bus_dmamap_t rl_tx_list_map; 640 struct rl_desc *rl_tx_list; 641 bus_dma_segment_t rl_tx_listseg; 642 }; 643 644 struct rl_softc { 645 struct device sc_dev; /* us, as a device */ 646 void * sc_ih; /* interrupt vectoring */ 647 bus_space_handle_t rl_bhandle; /* bus space handle */ 648 bus_space_tag_t rl_btag; /* bus space tag */ 649 bus_dma_tag_t sc_dmat; 650 bus_dma_segment_t sc_rx_seg; 651 bus_dmamap_t sc_rx_dmamap; 652 struct arpcom sc_arpcom; /* interface info */ 653 struct mii_data sc_mii; /* MII information */ 654 u_int8_t rl_type; 655 int rl_eecmd_read; 656 void *sc_sdhook; /* shutdownhook */ 657 void *sc_pwrhook; 658 int rl_txthresh; 659 int sc_flags; /* misc flags */ 660 struct rl_chain_data rl_cdata; 661 struct timeout sc_tick_tmo; 662 663 struct rl_list_data rl_ldata; 664 struct mbuf *rl_head; 665 struct mbuf *rl_tail; 666 u_int32_t rl_rxlenmask; 667 int rl_testmode; 668 struct timeout timer_handle; 669 }; 670 671 #define RL_ATTACHED 0x00000001 /* attach has succeeded */ 672 #define RL_ENABLED 0x00000002 /* chip is enabled */ 673 #define RL_IS_ENABLED(sc) ((sc)->sc_flags & RL_ENABLED) 674 675 /* 676 * register space access macros 677 */ 678 #define CSR_WRITE_4(sc, csr, val) \ 679 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val) 680 #define CSR_WRITE_2(sc, csr, val) \ 681 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val) 682 #define CSR_WRITE_1(sc, csr, val) \ 683 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val) 684 685 #define CSR_READ_4(sc, csr) \ 686 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr) 687 #define CSR_READ_2(sc, csr) \ 688 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr) 689 #define CSR_READ_1(sc, csr) \ 690 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr) 691 692 #define RL_TIMEOUT 1000 693 694 /* 695 * General constants that are fun to know. 696 * 697 * RealTek PCI vendor ID 698 */ 699 #define RT_VENDORID 0x10EC 700 701 /* 702 * RealTek chip device IDs. 703 */ 704 #define RT_DEVICEID_8129 0x8129 705 #define RT_DEVICEID_8139 0x8139 706 707 /* 708 * Accton PCI vendor ID 709 */ 710 #define ACCTON_VENDORID 0x1113 711 712 /* 713 * Accton MPX 5030/5038 device ID. 714 */ 715 #define ACCTON_DEVICEID_5030 0x1211 716 717 /* 718 * Delta Electronics Vendor ID. 719 */ 720 #define DELTA_VENDORID 0x1500 721 722 /* 723 * Delta device IDs. 724 */ 725 #define DELTA_DEVICEID_8139 0x1360 726 727 /* 728 * Addtron vendor ID. 729 */ 730 #define ADDTRON_VENDORID 0x4033 731 732 /* 733 * Addtron device IDs. 734 */ 735 #define ADDTRON_DEVICEID_8139 0x1360 736 737 /* D-Link Vendor ID */ 738 #define DLINK_VENDORID 0x1186 739 740 /* D-Link device IDs */ 741 #define DLINK_DEVICEID_8139 0x1300 742 #define DLINK_DEVICEID_8139_2 0x1340 743 744 /* Abocom device IDs */ 745 #define ABOCOM_DEVICEID_8139 0xab06 746 747 /* 748 * PCI low memory base and low I/O base register, and 749 * other PCI registers. Note: some are only available on 750 * the 3c905B, in particular those that related to power management. 751 */ 752 753 #define RL_PCI_VENDOR_ID 0x00 754 #define RL_PCI_DEVICE_ID 0x02 755 #define RL_PCI_COMMAND 0x04 756 #define RL_PCI_STATUS 0x06 757 #define RL_PCI_CLASSCODE 0x09 758 #define RL_PCI_LATENCY_TIMER 0x0D 759 #define RL_PCI_HEADER_TYPE 0x0E 760 #define RL_PCI_LOIO 0x10 761 #define RL_PCI_LOMEM 0x14 762 #define RL_PCI_BIOSROM 0x30 763 #define RL_PCI_INTLINE 0x3C 764 #define RL_PCI_INTPIN 0x3D 765 #define RL_PCI_MINGNT 0x3E 766 #define RL_PCI_MINLAT 0x0F 767 #define RL_PCI_RESETOPT 0x48 768 #define RL_PCI_EEPROM_DATA 0x4C 769 770 #define RL_PCI_CAPID 0x50 /* 8 bits */ 771 #define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 772 #define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 773 #define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 774 775 #define RL_PSTATE_MASK 0x0003 776 #define RL_PSTATE_D0 0x0000 777 #define RL_PSTATE_D1 0x0002 778 #define RL_PSTATE_D2 0x0002 779 #define RL_PSTATE_D3 0x0003 780 #define RL_PME_EN 0x0010 781 #define RL_PME_STATUS 0x8000 782 783 extern int rl_attach(struct rl_softc *); 784 extern int rl_detach(struct rl_softc *); 785 extern int rl_intr(void *); 786 extern void rl_setmulti(struct rl_softc *); 787