1 /*	$OpenBSD: if_ralreg.h,v 1.5 2005/04/01 13:13:43 damien Exp $  */
2 
3 /*-
4  * Copyright (c) 2005
5  *	Damien Bergamini <damien.bergamini@free.fr>
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #define RAL_RX_DESC_SIZE	(sizeof (struct ural_rx_desc))
21 #define RAL_TX_DESC_SIZE	(sizeof (struct ural_tx_desc))
22 
23 #define RAL_CONFIG_NO	1
24 #define RAL_IFACE_INDEX 0
25 
26 #define RAL_WRITE_MAC		0x02
27 #define RAL_READ_MAC		0x03
28 #define RAL_WRITE_MULTI_MAC	0x06
29 #define RAL_READ_MULTI_MAC	0x07
30 #define RAL_READ_EEPROM		0x09
31 
32 /*
33  * MAC registers.
34  */
35 #define RAL_MAC_CSR0	0x0400	/* ASIC Version */
36 #define RAL_MAC_CSR1	0x0402	/* System control */
37 #define RAL_MAC_CSR2	0x0404	/* MAC addr0 */
38 #define RAL_MAC_CSR3	0x0406	/* MAC addr1 */
39 #define RAL_MAC_CSR4	0x0408	/* MAC addr2 */
40 #define RAL_MAC_CSR5	0x040a	/* BSSID0 */
41 #define RAL_MAC_CSR6	0x040c	/* BSSID1 */
42 #define RAL_MAC_CSR7	0x040e	/* BSSID2 */
43 #define RAL_MAC_CSR8	0x0410	/* Max frame length */
44 #define RAL_MAC_CSR9	0x0412	/* Timer control */
45 #define RAL_MAC_CSR11	0x0416	/* IFS */
46 #define RAL_MAC_CSR12	0x0418	/* EIFS */
47 #define RAL_MAC_CSR13	0x041a	/* Power mode0 */
48 #define RAL_MAC_CSR14	0x041c	/* Power mode1 */
49 #define RAL_MAC_CSR15	0x041e	/* Power saving transition0 */
50 #define RAL_MAC_CSR16	0x0420	/* Power saving transition1 */
51 #define RAL_MAC_CSR17	0x0422	/* Power state control */
52 #define RAL_MAC_CSR18	0x0424	/* Auto wake-up control */
53 #define RAL_MAC_CSR19	0x0426	/* GPIO control */
54 #define RAL_MAC_CSR20	0x0428	/* LED control0 */
55 #define RAL_MAC_CSR22	0x042c	/* XXX not documented */
56 
57 /*
58  * Tx/Rx Registers.
59  */
60 #define RAL_TXRX_CSR0	0x0440	/* Security control */
61 #define RAL_TXRX_CSR2	0x0444	/* Rx control */
62 #define RAL_TXRX_CSR5	0x044a	/* CCK Tx BBP ID0 */
63 #define RAL_TXRX_CSR6	0x044c	/* CCK Tx BBP ID1 */
64 #define RAL_TXRX_CSR7	0x044e	/* OFDM Tx BBP ID0 */
65 #define RAL_TXRX_CSR8	0x0450	/* OFDM Tx BBP ID1 */
66 #define RAL_TXRX_CSR11	0x0456	/* Auto responder basic rate */
67 #define RAL_TXRX_CSR18	0x0464	/* Beacon interval */
68 #define RAL_TXRX_CSR19	0x0466	/* Beacon/sync control */
69 #define RAL_TXRX_CSR20	0x0468	/* Beacon alignment */
70 #define RAL_TXRX_CSR21	0x046a	/* XXX not documented */
71 
72 /*
73  * Security registers.
74  */
75 #define RAL_SEC_CSR0	0x0480	/* Shared key 0, word 0 */
76 
77 /*
78  * PHY registers.
79  */
80 #define RAL_PHY_CSR2	0x04c4	/* Tx MAC configuration */
81 #define RAL_PHY_CSR4	0x04c8	/* Interface configuration */
82 #define RAL_PHY_CSR5	0x04ca	/* BBP Pre-Tx CCK */
83 #define RAL_PHY_CSR6	0x04cc	/* BBP Pre-Tx OFDM */
84 #define RAL_PHY_CSR7	0x04ce	/* BBP serial control */
85 #define RAL_PHY_CSR8	0x04d0	/* BBP serial status */
86 #define RAL_PHY_CSR9	0x04d2	/* RF serial control0 */
87 #define RAL_PHY_CSR10	0x04d4	/* RF serial control1 */
88 
89 /*
90  * Statistics registers.
91  */
92 #define RAL_STA_CSR0	0x04e0	/* FCS error */
93 
94 
95 #define RAL_DISABLE_RX		(1 << 0)
96 #define RAL_DROP_CRC_ERROR	(1 << 1)
97 #define RAL_DROP_PHY_ERROR	(1 << 2)
98 #define RAL_DROP_CTL		(1 << 3)
99 #define RAL_DROP_NOT_TO_ME	(1 << 4)
100 #define RAL_DROP_TODS		(1 << 5)
101 #define RAL_DROP_VERSION_ERROR	(1 << 6)
102 #define RAL_DROP_MULTICAST	(1 << 9)
103 #define RAL_DROP_BROADCAST	(1 << 10)
104 
105 #define RAL_HOST_READY	(1 << 2)
106 #define RAL_RESET_ASIC	(1 << 0)
107 #define RAL_RESET_BBP	(1 << 1)
108 
109 #define RAL_ENABLE_TSF			(1 << 0)
110 #define RAL_ENABLE_TSF_SYNC(x)		(((x) & 0x3) << 1)
111 #define RAL_ENABLE_TBCN			(1 << 3)
112 #define RAL_ENABLE_BEACON_GENERATOR	(1 << 4)
113 
114 #define RAL_RF_AWAKE	(3 << 7)
115 #define RAL_BBP_AWAKE	(3 << 5)
116 
117 #define RAL_BBP_WRITE	(1 << 15)
118 #define RAL_BBP_BUSY	(1 << 0)
119 
120 #define RAL_RF1_AUTOTUNE	0x08000
121 #define RAL_RF3_AUTOTUNE	0x00040
122 
123 #define RAL_RF_2522	0x00
124 #define RAL_RF_2523	0x01
125 #define RAL_RF_2524	0x02
126 #define RAL_RF_2525	0x03
127 #define RAL_RF_2525E	0x04
128 #define RAL_RF_2526	0x05
129 /* dual-band RF */
130 #define RAL_RF_5222	0x10
131 
132 #define RAL_BBP_VERSION	0
133 #define RAL_BBP_TX	2
134 #define RAL_BBP_RX	14
135 
136 #define RAL_BBP_ANTA		0x00
137 #define RAL_BBP_DIVERSITY	0x01
138 #define RAL_BBP_ANTB		0x02
139 #define RAL_BBP_ANTMASK		0x03
140 #define RAL_BBP_FLIPIQ		0x04
141 
142 #define RAL_JAPAN_FILTER	0x08
143 
144 struct ural_tx_desc {
145 	uint32_t	flags;
146 #define RAL_TX_RETRY(x)		((x) << 4)
147 #define RAL_TX_MORE_FRAG	(1 << 8)
148 #define RAL_TX_ACK		(1 << 9)
149 #define RAL_TX_TIMESTAMP	(1 << 10)
150 #define RAL_TX_OFDM		(1 << 11)
151 #define RAL_TX_NEWSEQ		(1 << 12)
152 
153 #define RAL_TX_IFS_MASK		0x00006000
154 #define RAL_TX_IFS_BACKOFF	(0 << 13)
155 #define RAL_TX_IFS_SIFS		(1 << 13)
156 #define RAL_TX_IFS_NEWBACKOFF	(2 << 13)
157 #define RAL_TX_IFS_NONE		(3 << 13)
158 
159 	uint16_t	wme;
160 #define RAL_LOGCWMAX(x)		(((x) & 0xf) << 12)
161 #define RAL_LOGCWMIN(x)		(((x) & 0xf) << 8)
162 #define RAL_AIFSN(x)		(((x) & 0x3) << 6)
163 #define RAL_IVOFFSET(x)		(((x) & 0x3f))
164 
165 	uint16_t	reserved;
166 	uint8_t		plcp_signal;
167 	uint8_t		plcp_service;
168 #define RAL_PLCP_LENGEXT	0x80
169 
170 	uint16_t	plcp_length;
171 	uint32_t	iv;
172 	uint32_t	eiv;
173 } __packed;
174 
175 struct ural_rx_desc {
176 	uint32_t	flags;
177 #define RAL_RX_CRC_ERROR	(1 << 5)
178 #define RAL_RX_PHY_ERROR	(1 << 7)
179 
180 	uint8_t		rate;
181 	uint8_t		rssi;
182 	uint16_t	reserved;
183 
184 	uint32_t	iv;
185 	uint32_t	eiv;
186 } __packed;
187 
188 #define RAL_RF_LOBUSY	(1 << 15)
189 #define RAL_RF_BUSY	(1 << 31)
190 #define RAL_RF_20BIT	(20 << 24)
191 
192 #define RAL_RF1	0
193 #define RAL_RF2	2
194 #define RAL_RF3	1
195 #define RAL_RF4	3
196 
197 #define RAL_EEPROM_ADDRESS	0x0004
198 #define RAL_EEPROM_TXPOWER	0x003c
199 #define RAL_EEPROM_CONFIG0	0x0016
200 #define RAL_EEPROM_BBP_BASE	0x001c
201