1 /** $MirOS: src/sys/dev/pci/pcireg.h,v 1.5 2011/02/22 20:13:43 bsiegert Exp $ */ 2 /* $NetBSD: pcireg.h,v 1.40 2003/03/25 21:56:20 thorpej Exp $ */ 3 /* $OpenBSD: pcireg.h,v 1.39 2010/12/05 15:15:14 kettenis Exp $ */ 4 /* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ 5 6 /* 7 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 8 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Charles Hannum. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _DEV_PCI_PCIREG_H_ 37 #define _DEV_PCI_PCIREG_H_ 38 39 /* 40 * Standardized PCI configuration information 41 * 42 * XXX This is not complete. 43 */ 44 45 #define PCI_CONFIG_SPACE_SIZE 0x100 46 #define PCIE_CONFIG_SPACE_SIZE 0x1000 47 48 /* 49 * Device identification register; contains a vendor ID and a device ID. 50 */ 51 #define PCI_ID_REG 0x00 52 53 typedef u_int16_t pci_vendor_id_t; 54 typedef u_int16_t pci_product_id_t; 55 56 #define PCI_VENDOR_SHIFT 0 57 #define PCI_VENDOR_MASK 0xffff 58 #define PCI_VENDOR(id) \ 59 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 60 61 #define PCI_PRODUCT_SHIFT 16 62 #define PCI_PRODUCT_MASK 0xffff 63 #define PCI_PRODUCT(id) \ 64 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 65 66 #define PCI_ID_CODE(vid,pid) \ 67 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 68 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) 69 70 /* 71 * Command and status register. 72 */ 73 #define PCI_COMMAND_STATUS_REG 0x04 74 75 #define PCI_COMMAND_IO_ENABLE 0x00000001 76 #define PCI_COMMAND_MEM_ENABLE 0x00000002 77 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 78 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 79 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 80 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 81 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 82 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 83 #define PCI_COMMAND_SERR_ENABLE 0x00000100 84 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 85 #define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 86 87 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 88 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 89 #define PCI_STATUS_UDF_SUPPORT 0x00400000 90 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 91 #define PCI_STATUS_PARITY_ERROR 0x01000000 92 #define PCI_STATUS_DEVSEL_FAST 0x00000000 93 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 94 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 95 #define PCI_STATUS_DEVSEL_MASK 0x06000000 96 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 97 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 98 #define PCI_STATUS_MASTER_ABORT 0x20000000 99 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 100 #define PCI_STATUS_PARITY_DETECT 0x80000000 101 102 #define PCI_COMMAND_STATUS_BITS \ 103 ("\020\01IO\02MEM\03MASTER\04SPECIAL\05INVALIDATE\06PALETTE\07PARITY"\ 104 "\010STEPPING\011SERR\012BACKTOBACK\025CAPLIST\026CLK66\027UDF"\ 105 "\030BACK2BACK_STAT\031PARITY_STAT\032DEVSEL_MEDIUM\033DEVSEL_SLOW"\ 106 "\034TARGET_TARGET_ABORT\035MASTER_TARGET_ABORT\036MASTER_ABORT"\ 107 "\037SPECIAL_ERROR\040PARITY_DETECT") 108 /* 109 * PCI Class and Revision Register; defines type and revision of device. 110 */ 111 #define PCI_CLASS_REG 0x08 112 113 typedef u_int8_t pci_class_t; 114 typedef u_int8_t pci_subclass_t; 115 typedef u_int8_t pci_interface_t; 116 typedef u_int8_t pci_revision_t; 117 118 #define PCI_CLASS_SHIFT 24 119 #define PCI_CLASS_MASK 0xff 120 #define PCI_CLASS(cr) \ 121 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 122 123 #define PCI_SUBCLASS_SHIFT 16 124 #define PCI_SUBCLASS_MASK 0xff 125 #define PCI_SUBCLASS(cr) \ 126 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 127 128 #define PCI_INTERFACE_SHIFT 8 129 #define PCI_INTERFACE_MASK 0xff 130 #define PCI_INTERFACE(cr) \ 131 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 132 133 #define PCI_REVISION_SHIFT 0 134 #define PCI_REVISION_MASK 0xff 135 #define PCI_REVISION(cr) \ 136 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 137 138 /* base classes */ 139 #define PCI_CLASS_PREHISTORIC 0x00 140 #define PCI_CLASS_MASS_STORAGE 0x01 141 #define PCI_CLASS_NETWORK 0x02 142 #define PCI_CLASS_DISPLAY 0x03 143 #define PCI_CLASS_MULTIMEDIA 0x04 144 #define PCI_CLASS_MEMORY 0x05 145 #define PCI_CLASS_BRIDGE 0x06 146 #define PCI_CLASS_COMMUNICATIONS 0x07 147 #define PCI_CLASS_SYSTEM 0x08 148 #define PCI_CLASS_INPUT 0x09 149 #define PCI_CLASS_DOCK 0x0a 150 #define PCI_CLASS_PROCESSOR 0x0b 151 #define PCI_CLASS_SERIALBUS 0x0c 152 #define PCI_CLASS_WIRELESS 0x0d 153 #define PCI_CLASS_I2O 0x0e 154 #define PCI_CLASS_SATCOM 0x0f 155 #define PCI_CLASS_CRYPTO 0x10 156 #define PCI_CLASS_DASP 0x11 157 #define PCI_CLASS_UNDEFINED 0xff 158 159 /* 0x00 prehistoric subclasses */ 160 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 161 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 162 163 /* 0x01 mass storage subclasses */ 164 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 165 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 166 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 167 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 168 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 169 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 170 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 171 #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 172 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 173 174 /* 0x02 network subclasses */ 175 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 176 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 177 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 178 #define PCI_SUBCLASS_NETWORK_ATM 0x03 179 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 180 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 181 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 182 #define PCI_SUBCLASS_NETWORK_MISC 0x80 183 184 /* 0x03 display subclasses */ 185 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 186 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 187 #define PCI_SUBCLASS_DISPLAY_3D 0x02 188 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 189 190 /* 0x04 multimedia subclasses */ 191 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 192 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 193 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 194 #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 195 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 196 197 /* 0x05 memory subclasses */ 198 #define PCI_SUBCLASS_MEMORY_RAM 0x00 199 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 200 #define PCI_SUBCLASS_MEMORY_MISC 0x80 201 202 /* 0x06 bridge subclasses */ 203 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 204 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 205 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 206 #define PCI_SUBCLASS_BRIDGE_MC 0x03 207 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 208 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 209 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 210 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 211 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 212 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 213 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 214 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 215 216 /* 0x07 communications subclasses */ 217 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 218 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 219 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 220 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 221 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 222 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 223 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 224 225 /* 0x08 system subclasses */ 226 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 227 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 228 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 229 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 230 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 231 #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 232 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 233 234 /* 0x09 input subclasses */ 235 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 236 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 237 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 238 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 239 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 240 #define PCI_SUBCLASS_INPUT_MISC 0x80 241 242 /* 0x0a dock subclasses */ 243 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 244 #define PCI_SUBCLASS_DOCK_MISC 0x80 245 246 /* 0x0b processor subclasses */ 247 #define PCI_SUBCLASS_PROCESSOR_386 0x00 248 #define PCI_SUBCLASS_PROCESSOR_486 0x01 249 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 250 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 251 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 252 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 253 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 254 255 /* 0x0c serial bus subclasses */ 256 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 257 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 258 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 259 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 260 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 261 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 262 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 263 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 264 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 265 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 266 267 /* 0x0d wireless subclasses */ 268 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 269 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 270 #define PCI_SUBCLASS_WIRELESS_RF 0x10 271 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 272 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 273 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 274 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 275 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 276 277 /* 0x0e I2O (Intelligent I/O) subclasses */ 278 #define PCI_SUBCLASS_I2O_STANDARD 0x00 279 280 /* 0x0f satellite communication subclasses */ 281 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 282 #define PCI_SUBCLASS_SATCOM_TV 0x01 283 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 284 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 285 #define PCI_SUBCLASS_SATCOM_DATA 0x04 286 287 /* 0x10 encryption/decryption subclasses */ 288 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 289 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 290 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 291 292 /* 0x11 data acquisition and signal processing subclasses */ 293 #define PCI_SUBCLASS_DASP_DPIO 0x00 294 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 295 #define PCI_SUBCLASS_DASP_SYNC 0x10 296 #define PCI_SUBCLASS_DASP_MGMT 0x20 297 #define PCI_SUBCLASS_DASP_MISC 0x80 298 299 /* 300 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 301 */ 302 #define PCI_BHLC_REG 0x0c 303 304 #define PCI_BIST_SHIFT 24 305 #define PCI_BIST_MASK 0xff 306 #define PCI_BIST(bhlcr) \ 307 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 308 309 #define PCI_HDRTYPE_SHIFT 16 310 #define PCI_HDRTYPE_MASK 0xff 311 #define PCI_HDRTYPE(bhlcr) \ 312 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 313 314 #define PCI_HDRTYPE_TYPE(bhlcr) \ 315 (PCI_HDRTYPE(bhlcr) & 0x7f) 316 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 317 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 318 319 #define PCI_LATTIMER_SHIFT 8 320 #define PCI_LATTIMER_MASK 0xff 321 #define PCI_LATTIMER(bhlcr) \ 322 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 323 324 #define PCI_CACHELINE_SHIFT 0 325 #define PCI_CACHELINE_MASK 0xff 326 #define PCI_CACHELINE(bhlcr) \ 327 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 328 329 /* config registers for header type 0 devices */ 330 331 #define PCI_MAPS 0x10 332 #define PCI_CARDBUSCIS 0x28 333 #define PCI_SUBVEND_0 0x2c 334 #define PCI_SUBDEV_0 0x2e 335 #define PCI_INTLINE 0x3c 336 #define PCI_INTPIN 0x3d 337 #define PCI_MINGNT 0x3e 338 #define PCI_MAXLAT 0x3f 339 340 /* config registers for header type 1 devices */ 341 342 #define PCI_SECSTAT_1 0 /**/ 343 344 #define PCI_PRIBUS_1 0x18 345 #define PCI_SECBUS_1 0x19 346 #define PCI_SUBBUS_1 0x1a 347 #define PCI_SECLAT_1 0x1b 348 349 #define PCI_IOBASEL_1 0x1c 350 #define PCI_IOLIMITL_1 0x1d 351 #define PCI_IOBASEH_1 0 /**/ 352 #define PCI_IOLIMITH_1 0 /**/ 353 354 #define PCI_MEMBASE_1 0x20 355 #define PCI_MEMLIMIT_1 0x22 356 357 #define PCI_PMBASEL_1 0x24 358 #define PCI_PMLIMITL_1 0x26 359 #define PCI_PMBASEH_1 0 /**/ 360 #define PCI_PMLIMITH_1 0 /**/ 361 362 #define PCI_BRIDGECTL_1 0 /**/ 363 364 #define PCI_SUBVEND_1 0x34 365 #define PCI_SUBDEV_1 0x36 366 367 /* config registers for header type 2 devices */ 368 369 #define PCI_SECSTAT_2 0x16 370 371 #define PCI_PRIBUS_2 0x18 372 #define PCI_SECBUS_2 0x19 373 #define PCI_SUBBUS_2 0x1a 374 #define PCI_SECLAT_2 0x1b 375 376 #define PCI_MEMBASE0_2 0x1c 377 #define PCI_MEMLIMIT0_2 0x20 378 #define PCI_MEMBASE1_2 0x24 379 #define PCI_MEMLIMIT1_2 0x28 380 #define PCI_IOBASE0_2 0x2c 381 #define PCI_IOLIMIT0_2 0x30 382 #define PCI_IOBASE1_2 0x34 383 #define PCI_IOLIMIT1_2 0x38 384 385 #define PCI_BRIDGECTL_2 0x3e 386 387 #define PCI_SUBVEND_2 0x40 388 #define PCI_SUBDEV_2 0x42 389 390 #define PCI_PCCARDIF_2 0x44 391 392 /* 393 * Mapping registers 394 */ 395 #define PCI_MAPREG_START 0x10 396 #define PCI_MAPREG_END 0x28 397 #define PCI_MAPREG_PPB_END 0x18 398 #define PCI_MAPREG_PCB_END 0x14 399 400 #define PCI_MAPREG_TYPE(mr) \ 401 ((mr) & PCI_MAPREG_TYPE_MASK) 402 #define PCI_MAPREG_TYPE_MASK 0x00000001 403 404 #define PCI_MAPREG_TYPE_MEM 0x00000000 405 #define PCI_MAPREG_TYPE_IO 0x00000001 406 407 #define PCI_MAPREG_MEM_TYPE(mr) \ 408 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 409 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 410 411 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 412 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 413 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 414 415 #define _PCI_MAPREG_TYPEBITS(reg) \ 416 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 417 reg & PCI_MAPREG_TYPE_MASK : \ 418 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 419 420 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 421 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 422 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 423 424 #define PCI_MAPREG_MEM_ADDR(mr) \ 425 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 426 #define PCI_MAPREG_MEM_SIZE(mr) \ 427 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 428 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 429 430 #define PCI_MAPREG_MEM64_ADDR(mr) \ 431 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 432 #define PCI_MAPREG_MEM64_SIZE(mr) \ 433 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 434 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 435 436 #define PCI_MAPREG_IO_ADDR(mr) \ 437 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 438 #define PCI_MAPREG_IO_SIZE(mr) \ 439 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 440 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 441 442 /* 443 * Cardbus CIS pointer (PCI rev. 2.1) 444 */ 445 #define PCI_CARDBUS_CIS_REG 0x28 446 447 /* 448 * Subsystem identification register; contains a vendor ID and a device ID. 449 * Types/macros for PCI_ID_REG apply. 450 * (PCI rev. 2.1) 451 */ 452 #define PCI_SUBSYS_ID_REG 0x2c 453 454 /* 455 * Expansion ROM Base Address register 456 * (PCI rev. 2.0) 457 */ 458 #define PCI_ROM_REG 0x30 459 460 #define PCI_ROM_ENABLE 0x00000001 461 #define PCI_ROM_ADDR_MASK 0xfffff800 462 #define PCI_ROM_ADDR(mr) \ 463 ((mr) & PCI_ROM_ADDR_MASK) 464 #define PCI_ROM_SIZE(mr) \ 465 (PCI_ROM_ADDR(mr) & -PCI_ROM_ADDR(mr)) 466 467 /* 468 * capabilities link list (PCI rev. 2.2) 469 */ 470 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 471 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 472 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 473 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 474 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 475 476 #define PCI_CAP_RESERVED 0x00 477 #define PCI_CAP_PWRMGMT 0x01 478 #define PCI_CAP_AGP 0x02 479 #define PCI_CAP_VPD 0x03 480 #define PCI_CAP_SLOTID 0x04 481 #define PCI_CAP_MSI 0x05 482 #define PCI_CAP_CPCI_HOTSWAP 0x06 483 #define PCI_CAP_PCIX 0x07 484 #define PCI_CAP_LDT 0x08 485 #define PCI_CAP_VENDSPEC 0x09 486 #define PCI_CAP_DEBUGPORT 0x0a 487 #define PCI_CAP_CPCI_RSRCCTL 0x0b 488 #define PCI_CAP_HOTPLUG 0x0c 489 #define PCI_CAP_AGP8 0x0e 490 #define PCI_CAP_SECURE 0x0f 491 #define PCI_CAP_PCIEXPRESS 0x10 492 #define PCI_CAP_MSIX 0x11 493 494 /* 495 * Vital Product Data; access via capability pointer (PCI rev 2.2). 496 */ 497 #define PCI_VPD_ADDRESS_MASK 0x7fff 498 #define PCI_VPD_ADDRESS_SHIFT 16 499 #define PCI_VPD_ADDRESS(ofs) \ 500 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 501 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 502 #define PCI_VPD_OPFLAG 0x80000000 503 504 /* 505 * Power Management Control Status Register; access via capability pointer. 506 */ 507 #define PCI_PMCSR 0x04 508 #define PCI_PMCSR_STATE_MASK 0x03 509 #define PCI_PMCSR_STATE_D0 0x00 510 #define PCI_PMCSR_STATE_D1 0x01 511 #define PCI_PMCSR_STATE_D2 0x02 512 #define PCI_PMCSR_STATE_D3 0x03 513 514 /* 515 * PCI Express; access via capability pointer. 516 */ 517 #define PCI_PCIE_XCAP 0x00 518 #define PCI_PCIE_XCAP_SI 0x01000000 519 #define PCI_PCIE_DCAP 0x04 520 #define PCI_PCIE_DCSR 0x08 521 #define PCI_PCIE_DCSR_ENA_NO_SNOOP 0x00000800 522 #define PCI_PCIE_LCAP 0x0c 523 #define PCI_PCIE_LCSR 0x10 524 #define PCI_PCIE_LCSR_ASPM_L0S 0x00000001 525 #define PCI_PCIE_LCSR_ASPM_L1 0x00000002 526 #define PCI_PCIE_LCSR_ES 0x00000080 527 #define PCI_PCIE_SLCAP 0x14 528 #define PCI_PCIE_SLCAP_ABP 0x00000001 529 #define PCI_PCIE_SLCAP_PCP 0x00000002 530 #define PCI_PCIE_SLCAP_MSP 0x00000004 531 #define PCI_PCIE_SLCAP_AIP 0x00000008 532 #define PCI_PCIE_SLCAP_PIP 0x00000010 533 #define PCI_PCIE_SLCAP_HPS 0x00000020 534 #define PCI_PCIE_SLCAP_HPC 0x00000040 535 #define PCI_PCIE_SLCSR 0x18 536 #define PCI_PCIE_SLCSR_ABE 0x00000001 537 #define PCI_PCIE_SLCSR_PFE 0x00000002 538 #define PCI_PCIE_SLCSR_MSE 0x00000004 539 #define PCI_PCIE_SLCSR_PDE 0x00000008 540 #define PCI_PCIE_SLCSR_CCE 0x00000010 541 #define PCI_PCIE_SLCSR_HPE 0x00000020 542 #define PCI_PCIE_SLCSR_ABP 0x00010000 543 #define PCI_PCIE_SLCSR_PFD 0x00020000 544 #define PCI_PCIE_SLCSR_MSC 0x00040000 545 #define PCI_PCIE_SLCSR_PDC 0x00080000 546 #define PCI_PCIE_SLCSR_CC 0x00100000 547 #define PCI_PCIE_SLCSR_MS 0x00200000 548 #define PCI_PCIE_SLCSR_PDS 0x00400000 549 #define PCI_PCIE_SLCSR_LACS 0x01000000 550 #define PCI_PCIE_RCSR 0x1c 551 552 /* 553 * Interrupt Configuration Register; contains interrupt pin and line. 554 */ 555 #define PCI_INTERRUPT_REG 0x3c 556 557 typedef u_int8_t pci_intr_pin_t; 558 typedef u_int8_t pci_intr_line_t; 559 560 #define PCI_INTERRUPT_PIN_SHIFT 8 561 #define PCI_INTERRUPT_PIN_MASK 0xff 562 #define PCI_INTERRUPT_PIN(icr) \ 563 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 564 565 #define PCI_INTERRUPT_LINE_SHIFT 0 566 #define PCI_INTERRUPT_LINE_MASK 0xff 567 #define PCI_INTERRUPT_LINE(icr) \ 568 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 569 570 #define PCI_MIN_GNT_SHIFT 16 571 #define PCI_MIN_GNT_MASK 0xff 572 #define PCI_MIN_GNT(icr) \ 573 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 574 575 #define PCI_MAX_LAT_SHIFT 24 576 #define PCI_MAX_LAT_MASK 0xff 577 #define PCI_MAX_LAT(icr) \ 578 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 579 580 #define PCI_INTERRUPT_PIN_NONE 0x00 581 #define PCI_INTERRUPT_PIN_A 0x01 582 #define PCI_INTERRUPT_PIN_B 0x02 583 #define PCI_INTERRUPT_PIN_C 0x03 584 #define PCI_INTERRUPT_PIN_D 0x04 585 #define PCI_INTERRUPT_PIN_MAX 0x04 586 587 /* 588 * Vital Product Data resource tags. 589 */ 590 struct pci_vpd_smallres { 591 uint8_t vpdres_byte0; /* length of data + tag */ 592 /* Actual data. */ 593 } __packed; 594 595 struct pci_vpd_largeres { 596 uint8_t vpdres_byte0; 597 uint8_t vpdres_len_lsb; /* length of data only */ 598 uint8_t vpdres_len_msb; 599 /* Actual data. */ 600 } __packed; 601 602 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 603 604 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 605 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 606 607 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 608 609 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 610 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 611 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 612 613 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 614 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 615 616 struct pci_vpd { 617 uint8_t vpd_key0; 618 uint8_t vpd_key1; 619 uint8_t vpd_len; /* length of data only */ 620 /* Actual data. */ 621 } __packed; 622 623 /* 624 * Recommended VPD fields: 625 * 626 * PN Part number of assembly 627 * FN FRU part number 628 * EC EC level of assembly 629 * MN Manufacture ID 630 * SN Serial Number 631 * 632 * Conditionally recommended VPD fields: 633 * 634 * LI Load ID 635 * RL ROM Level 636 * RM Alterable ROM Level 637 * NA Network Address 638 * DD Device Driver Level 639 * DG Diagnostic Level 640 * LL Loadable Microcode Level 641 * VI Vendor ID/Device ID 642 * FU Function Number 643 * SI Subsystem Vendor ID/Subsystem ID 644 * 645 * Additional VPD fields: 646 * 647 * Z0-ZZ User/Product Specific 648 */ 649 650 #endif /* _DEV_PCI_PCIREG_H_ */ 651