1 /* $OpenBSD: smc91cxxreg.h,v 1.2 2001/06/27 05:44:52 nate Exp $ */ 2 /* $NetBSD: smc91cxxreg.h,v 1.2 1997/09/02 00:10:58 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Gardner Buchanan. 19 * 4. The name of Gardner Buchanan may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * from FreeBSD Id: if_snreg.h,v 1.4 1996/03/18 15:47:30 gardner Exp 35 */ 36 37 /* 38 * This file contains register information and access macros for 39 * the SMC91xxx chipset. 40 * 41 * Information contained in this file was obtained from the SMC91C92 42 * and SMC91C94 manuals from SMC. You will need one of these in order 43 * to make any meaningful changes to this driver. Information about 44 * obtaining one can be found at http://www.smc.com in the components 45 * division. 46 * 47 * This FreeBSD driver is derived in part from the smc9194 Linux driver 48 * by Erik Stahlman. 49 */ 50 51 52 /* 53 * Wait time for memory to be free. This probably shouldn't be 54 * tuned that much, as waiting for this means nothing else happens 55 * in the system 56 */ 57 #define MEMORY_WAIT_TIME 1000 58 59 60 /* The SMC91xxx uses 16 I/O ports */ 61 #define SMC_IOSIZE 16 62 63 64 /* 65 * A description of the SMC registers is probably in order here, 66 * although for details, the SMC datasheet is invaluable. 67 * The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet 68 * Controller With RAM", Rev. 12/0/94. Constant definitions I give 69 * here are loosely based on the mnemonic names given to them in the 70 * data sheet, but there are many exceptions. 71 * 72 * Basically, the chip has 4 banks of registers (0 to 3), which 73 * are accessed by writing a number into the BANK_SELECT register 74 * (I also use a SMC_SELECT_BANK macro for this). Registers are 75 * either Byte or Word sized. My constant definitions end in _B 76 * or _W as appropriate. 77 * 78 * The banks are arranged so that for most purposes, bank 2 is all 79 * that is needed for normal run time tasks. 80 */ 81 82 83 /* 84 * Bank Select Register. This also doubles as 85 * a chip identification register. This register 86 * is mapped at the same position in all banks. 87 */ 88 #define BANK_SELECT_REG_W 0x0e 89 #define BSR_DETECT_MASK 0xff00 90 #define BSR_DETECT_VALUE 0x3300 91 92 93 /* 94 * BANK 0 95 */ 96 97 /* 98 * Transmit Control Register controls some aspects of the transmit 99 * behavior of the Ethernet Protocol Handler. 100 */ 101 #define TXMIT_CONTROL_REG_W 0x00 102 103 #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ 104 #define TCR_LOOP 0x0002 /* Enable internal analogue loopback */ 105 #define TCR_FORCOL 0x0004 /* Force Collision on next TX */ 106 #define TCR_PAD_ENABLE 0x0080 /* Pad short packets to 64 bytes */ 107 #define TCR_NOCRC 0x0100 /* Do not append CRC */ 108 #define TCR_MON_CSN 0x0400 /* monitors the carrier status */ 109 #define TCR_FDUPLX 0x0800 /* receive packets sent out */ 110 #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ 111 #define TCR_EPH_LOOP 0x2000 /* Enable internal digital loopback */ 112 113 114 /* 115 * Status of the last transmitted frame and instantaneous status of 116 * the Ethernet Protocol Handler jumbled together. In auto-release 117 * mode this information is simply discarded after each TX. This info 118 * is copied to the status word of in-memory packets after transmit 119 * where relevent statuses can be checked. 120 */ 121 #define EPH_STATUS_REG_W 0x02 122 123 #define EPHSR_TX_SUC 0x0001 /* Transmit was successful */ 124 #define EPHSR_SNGLCOL 0x0002 /* Single collision occurred */ 125 #define EPHSR_MULCOL 0x0004 /* Multiple Collisions occurred */ 126 #define EPHSR_LTX_MULT 0x0008 /* Transmit was a multicast */ 127 #define EPHSR_16COL 0x0010 /* 16 Collisions occurred, TX disabled */ 128 #define EPHSR_SQET 0x0020 /* SQE Test failed, TX disabled */ 129 #define EPHSR_LTX_BRD 0x0040 /* Transmit was a broadcast */ 130 #define EPHSR_DEFR 0x0080 /* TX deferred due to carrier det. */ 131 #define EPHSR_LATCOL 0x0200 /* Late collision detected, TX disabled */ 132 #define EPHSR_LOST_CAR 0x0400 /* Lost carrier sense, TX disabled */ 133 #define EPHSR_EXC_DEF 0x0800 /* Excessive deferrals in TX >2 MAXETHER 134 * times */ 135 #define EPHSR_CTR_ROL 0x1000 /* Some ECR Counter(s) rolled over */ 136 #define EPHSR_RX_OVRN 0x2000 /* Receiver overrun, packets dropped */ 137 #define EPHSR_LINK_OK 0x4000 /* Link integrity is OK */ 138 #define EPHSR_TXUNRN 0x8000 /* Transmit underrun */ 139 140 141 /* 142 * Receiver Control Register controls some aspects of the receive 143 * behavior of the Ethernet Protocol Handler. 144 */ 145 #define RECV_CONTROL_REG_W 0x04 146 147 #define RCR_RX_ABORT 0x0001 /* Received huge packet */ 148 #define RCR_PROMISC 0x0002 /* enable promiscuous mode */ 149 #define RCR_ALMUL 0x0004 /* receive all multicast packets */ 150 #define RCR_ENABLE 0x0100 /* IFF this is set, we can receive packets */ 151 #define RCR_STRIP_CRC 0x0200 /* strips CRC */ 152 #define RCR_GAIN_BITS 0x0c00 /* PLL Gain control (for testing) */ 153 #define RCR_FILT_CAR 0x4000 /* Enable 12 bit carrier filter */ 154 #define RCR_SOFTRESET 0x8000 /* Resets the EPH logic */ 155 156 157 /* 158 * TX Statistics counters 159 */ 160 #define COUNTER_REG_W 0x06 161 162 #define ECR_COLN_MASK 0x000f /* Vanilla collisions */ 163 #define ECR_MCOLN_MASK 0x00f0 /* Multiple collisions */ 164 #define ECR_DTX_MASK 0x0f00 /* Deferred transmits */ 165 #define ECR_EXDTX_MASK 0xf000 /* Excessively deferred transmits */ 166 167 168 /* 169 * Memory Information 170 */ 171 #define MEM_INFO_REG_W 0x08 172 173 #define MIR_FREE_MASK 0xff00 /* Free memory pages available */ 174 #define MIR_TOTAL_MASK 0x00ff /* Total memory pages available */ 175 176 177 /* 178 * Memory Configuration 179 */ 180 #define MEM_CFG_REG_W 0x0a 181 182 #define MCR_TXRSV_MASK 0x001f /* Count of pages reserved for transmit */ 183 184 185 /* 186 * Bank 0, Register 0x0c is unused in the SMC91C92 187 */ 188 189 190 /* 191 * BANK 1 192 */ 193 194 /* 195 * Adapter configuration 196 */ 197 #define CONFIG_REG_W 0x00 198 199 #define CR_INT_SEL0 0x0002 /* Interrupt selector */ 200 #define CR_INT_SEL1 0x0004 /* Interrupt selector */ 201 #define CR_DIS_LINK 0x0040 /* Disable 10BaseT Link Test */ 202 #define CR_16BIT 0x0080 /* Bus width */ 203 #define CR_AUI_SELECT 0x0100 /* Use external (AUI) Transceiver */ 204 #define CR_SET_SQLCH 0x0200 /* Squelch level */ 205 #define CR_FULL_STEP 0x0400 /* AUI signalling mode */ 206 #define CR_NOW_WAIT_ST 0x1000 /* Disable bus wait states */ 207 208 209 /* 210 * The contents of this port are used by the adapter 211 * to decode its I/O address. We use it as a varification 212 * that the adapter is detected properly when probing. 213 */ 214 #define BASE_ADDR_REG_W 0x02 /* The selected I/O Base addr. */ 215 216 217 /* 218 * These registers hold the Ethernet MAC address. 219 */ 220 #define IAR_ADDR0_REG_W 0x04 /* My Ethernet address */ 221 #define IAR_ADDR1_REG_W 0x06 /* My Ethernet address */ 222 #define IAR_ADDR2_REG_W 0x08 /* My Ethernet address */ 223 224 225 /* 226 * General purpose register used for talking to the EEPROM. 227 */ 228 #define GENERAL_REG_W 0x0a 229 230 231 /* 232 * Control register used for talking to the EEPROM and 233 * setting some EPH functions. 234 */ 235 #define CONTROL_REG_W 0x0c 236 237 #define CTR_STORE 0x0001 /* Store something to EEPROM */ 238 #define CTR_RELOAD 0x0002 /* Read EEPROM into registers */ 239 #define CTR_EEPROM_SEL 0x0004 /* Select registers for Reload/Store */ 240 #define CTR_TE_ENABLE 0x0020 /* Enable TX Error detection via EPH_INT */ 241 #define CTR_CR_ENABLE 0x0040 /* Enable Counter Rollover via EPH_INT */ 242 #define CTR_LE_ENABLE 0x0080 /* Enable Link Error detection via EPH_INT */ 243 #define CTR_AUTO_RELEASE 0x0800 /* Enable auto release mode for TX */ 244 #define CTR_POWERDOWN 0x2000 /* Enter powerdown mode */ 245 #define CTR_RCV_BAD 0x4000 /* Enable receipt of frames with bad CRC */ 246 247 248 /* 249 * BANK 2 250 */ 251 252 253 /* 254 * Memory Management Unit Control Register 255 * Controls allocation of memory to receive and 256 * transmit functions. 257 */ 258 #define MMU_CMD_REG_W 0x00 259 260 #define MMUCR_BUSY 0x0001 /* MMU busy performing a release */ 261 262 /* 263 * MMU Commands: 264 */ 265 #define MMUCR_NOP 0x0000 /* Do nothing */ 266 #define MMUCR_ALLOC 0x0020 /* Or with number of 256 byte packets - 1 */ 267 #define MMUCR_RESET 0x0040 /* Reset MMU State */ 268 #define MMUCR_REMOVE 0x0060 /* Dequeue (but not free) current RX packet */ 269 #define MMUCR_RELEASE 0x0080 /* Dequeue and free the current RX packet */ 270 #define MMUCR_FREEPKT 0x00a0 /* Release packet in PNR register */ 271 #define MMUCR_ENQUEUE 0x00c0 /* Enqueue the packet for transmit */ 272 #define MMUCR_RESETTX 0x00e0 /* Reset transmit queues */ 273 274 /* 275 * Packet Number at TX Area 276 */ 277 #define PACKET_NUM_REG_B 0x02 278 279 /* 280 * Packet number resulting from MMUCR_ALLOC 281 */ 282 #define ALLOC_RESULT_REG_B 0x03 283 #define ARR_FAILED 0x80 284 285 /* 286 * Transmit and receive queue heads 287 */ 288 #define FIFO_PORTS_REG_W 0x04 289 #define FIFO_REMPTY 0x8000 290 #define FIFO_TEMPTY 0x0080 291 #define FIFO_RX_MASK 0x7f00 292 #define FIFO_TX_MASK 0x007f 293 294 295 /* 296 * The address within the packet for reading/writing. The 297 * PTR_RCV bit is tricky. When PTR_RCV==1, the packet number 298 * to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK. 299 * When PTR_RCV==0, the packet number to be written is found 300 * in the PACKET_NUM_REG_B. 301 */ 302 #define POINTER_REG_W 0x06 303 304 #define PTR_READ 0x2000 /* Intended access mode */ 305 #define PTR_AUTOINC 0x4000 /* Do auto inc after read/write */ 306 #define PTR_RCV 0x8000 /* FIFO_RX is packet, otherwise PNR is packet */ 307 308 /* 309 * Data I/O register to be used in conjunction with 310 * The pointer register to read and write data from the 311 * card. The same register can be used for byte and word 312 * ops. 313 */ 314 #define DATA_REG_W 0x08 315 #define DATA_REG_B 0x08 316 #define DATA_1_REG_B 0x08 317 #define DATA_2_REG_B 0x0a 318 319 320 /* 321 * Sense interrupt status (READ) 322 */ 323 #define INTR_STAT_REG_B 0x0c 324 325 326 /* 327 * Acknowledge interrupt sources (WRITE) 328 */ 329 #define INTR_ACK_REG_B 0x0c 330 331 332 /* 333 * Interrupt mask. Bit set indicates interrupt allowed. 334 */ 335 #define INTR_MASK_REG_B 0x0d 336 337 /* 338 * Interrupts 339 */ 340 #define IM_RCV_INT 0x01 /* A packet has been received */ 341 #define IM_TX_INT 0x02 /* Packet TX complete */ 342 #define IM_TX_EMPTY_INT 0x04 /* No packets left to TX */ 343 #define IM_ALLOC_INT 0x08 /* Memory allocation completed */ 344 #define IM_RX_OVRN_INT 0x10 /* Receiver was overrun */ 345 #define IM_EPH_INT 0x20 /* Misc. EPH conditions (see CONTROL_REG_W) */ 346 #define IM_ERCV_INT 0x40 /* not on SMC9192 */ 347 348 349 /* 350 * BANK 3 351 */ 352 353 354 /* 355 * Multicast subscriptions. 356 * The multicast handling in the SMC90Cxx is quite complicated. A table 357 * of multicast address subscriptions is provided and a clever way of 358 * speeding the search of that table by hashing is implemented in the 359 * hardware. I have ignored this and simply subscribed to all multicasts 360 * and let the kernel deal with the results. 361 */ 362 #define MULTICAST1_REG_W 0x00 363 #define MULTICAST2_REG_W 0x02 364 #define MULTICAST3_REG_W 0x04 365 #define MULTICAST4_REG_W 0x06 366 367 /* 368 * These registers do not exist on SMC9192, or at least 369 * are not documented in the SMC91C92 data sheet. 370 * The REVISION_REG_W register does however seem to work. 371 */ 372 #define MGMT_REG_W 0x08 373 374 #define REVISION_REG_W 0x0a /* (hi: chip id low: rev #) */ 375 #define RR_REV(x) ((x) & 0x0f) 376 #define RR_ID(x) (((x) >> 4) & 0x0f) 377 378 #define ERCV_REG_W 0x0c 379 380 /* 381 * These are constants expected to be found in the 382 * chip id register. 383 */ 384 #define CHIP_9190 3 385 #define CHIP_9194 4 386 #define CHIP_9195 5 387 #define CHIP_91100 7 388 389 390 /* 391 * When packets are stuffed into the card or sucked out of the card 392 * they are set up more or less as follows: 393 * 394 * Addr msbyte lsbyte 395 * 00 SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status 396 * 02 RRRRR - RESERVED (unused) 397 * 02 CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored) 398 * 04 DDDDDDDD DDDDDDDD - DESTINATION ADDRESS 399 * 06 DDDDDDDD DDDDDDDD (48 bit Ethernet MAC Address) 400 * 08 DDDDDDDD DDDDDDDD 401 * 0A SSSSSSSS SSSSSSSS - SOURCE ADDRESS 402 * 0C SSSSSSSS SSSSSSSS (48 bit Ethernet MAC Address) 403 * 0E SSSSSSSS SSSSSSSS 404 * 10 PPPPPPPP PPPPPPPP 405 * .. PPPPPPPP PPPPPPPP 406 * C-2 CCCCCCCC - CONTROL BYTE 407 * C-2 PPPPPPPP - Last data byte (If odd length) 408 * 409 * The STATUS_WORD is derived from the EPH_STATUS_REG_W register 410 * during transmit and is composed of another set of bits described 411 * below during receive. 412 */ 413 414 415 /* 416 * Receive status bits. These values are found in the status word 417 * field of a received packet. For receive packets I use the RS_ODDFRAME 418 * to detect whether a frame has an extra byte on it. The CTLB_ODD 419 * bit of the control byte tells the same thing. 420 */ 421 #define RS_MULTICAST 0x0001 /* Packet is multicast */ 422 #define RS_HASH_MASK 0x007e /* Mask of multicast hash value */ 423 #define RS_TOOSHORT 0x0400 /* Frame was a runt, <64 bytes */ 424 #define RS_TOOLONG 0x0800 /* Frame was giant, >1518 */ 425 #define RS_ODDFRAME 0x1000 /* Frame is odd lengthed */ 426 #define RS_BADCRC 0x2000 /* Frame had CRC error */ 427 #define RS_ALGNERR 0x8000 /* Frame had alignment error */ 428 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 429 430 #define RLEN_MASK 0x07ff /* Significant length bits in RX length */ 431 432 /* 433 * The control byte has the following significant bits. 434 * For transmit, the CTLB_ODD bit specifies whether an extra byte 435 * is present in the frame. Bit 0 of the byte count field is 436 * ignored. I just pad every frame to even length and forget about 437 * it. 438 */ 439 #define CTLB_CRC 0x10 /* Add CRC for this packet (TX only) */ 440 #define CTLB_ODD 0x20 /* The packet length is ODD */ 441