1 /* ISDN4BSD code */ 2 /* $NetBSD: iwicreg.h,v 1.2 2002/10/23 14:57:15 pooka Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Dave Boyce. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 *--------------------------------------------------------------------------- 29 * 30 * i4b_iwic - isdn4bsd Winbond W6692 driver 31 * ---------------------------------------- 32 * 33 * $FreeBSD: src/sys/i4b/layer1/iwic/i4b_iwic.h,v 1.1 2000/10/09 13:28:59 hm Exp $ 34 * 35 * last edit-date: [Sun Jan 21 11:08:44 2001] 36 * 37 *---------------------------------------------------------------------------*/ 38 39 #ifndef _IWICREG_H_ 40 #define _IWICREG_H_ 41 42 #define IWIC_BCH_A 0 /* channel A */ 43 #define IWIC_BCH_B 1 /* channel B */ 44 45 /*---------------------------------------------------------------------------* 46 * FIFO depths 47 *---------------------------------------------------------------------------*/ 48 #define IWIC_DCHAN_FIFO_LEN 64 49 #define IWIC_BCHAN_FIFO_LEN 64 50 51 /*---------------------------------------------------------------------------* 52 * D-Channel register offsets 53 *---------------------------------------------------------------------------*/ 54 #define D_RFIFO 0x00 /* D channel receive FIFO */ 55 #define D_XFIFO 0x04 /* D channel transmit FIFO */ 56 #define D_CMDR 0x08 /* D channel command register */ 57 #define D_MODE 0x0c /* D channel mode control */ 58 #define D_TIMR 0x10 /* D channel timer control */ 59 #define D_EXIR 0x1c /* D channel extended interrupt */ 60 #define D_EXIM 0x20 /* D channel extended interrupt mask */ 61 #define D_STAR 0x24 /* D channel status register */ 62 #define D_RSTA 0x28 /* D channel receive status */ 63 #define D_SAM 0x2c /* D channel address mask 1 */ 64 #define D_SAP1 0x30 /* D channel individual SAPI 1 */ 65 #define D_SAP2 0x34 /* D channel individual SAPI 2 */ 66 #define D_TAM 0x38 /* D channel address mask 2 */ 67 #define D_TEI1 0x3c /* D channel individual TEI 1 */ 68 #define D_TEI2 0x40 /* D channel individual TEI 2 */ 69 #define D_RBCH 0x44 /* D channel receive frame byte count high */ 70 #define D_RBCL 0x48 /* D channel receive frame byte count low */ 71 #define D_CTL 0x54 /* D channel control register */ 72 73 /*---------------------------------------------------------------------------* 74 * B-channel base offsets 75 *---------------------------------------------------------------------------*/ 76 #define B1_CHAN_OFFSET 0x80 /* B1 channel offset */ 77 #define B2_CHAN_OFFSET 0xc0 /* B2 channel offset */ 78 79 /*---------------------------------------------------------------------------* 80 * B-channel register offsets, from base 81 *---------------------------------------------------------------------------*/ 82 #define B_RFIFO 0x00 /* B channel receive FIFO */ 83 #define B_XFIFO 0x04 /* B channel transmit FIFO */ 84 #define B_CMDR 0x08 /* B channel command register */ 85 #define B_MODE 0x0c /* B channel mode control */ 86 #define B_EXIR 0x10 /* B channel extended interrupt */ 87 #define B_EXIM 0x14 /* B channel extended interrupt mask */ 88 #define B_STAR 0x18 /* B channel status register */ 89 #define B_ADM1 0x1c /* B channel address mask 1 */ 90 #define B_ADM2 0x20 /* B channel address mask 2 */ 91 #define B_ADR1 0x24 /* B channel address 1 */ 92 #define B_ADR2 0x28 /* B channel address 2 */ 93 #define B_RBCL 0x2c /* B channel receive frame byte count high */ 94 #define B_RBCH 0x30 /* B channel receive frame byte count low */ 95 96 /*---------------------------------------------------------------------------* 97 * Remaining control register offsets. 98 *---------------------------------------------------------------------------*/ 99 #define ISTA 0x14 /* Interrupt status register */ 100 #define IWIC_IMASK 0x18 /* Interrupt mask register */ 101 #define TIMR2 0x4c /* Timer 2 */ 102 #define L1_RC 0x50 /* GCI layer 1 ready code */ 103 #define CIR 0x58 /* Command/Indication receive */ 104 #define CIX 0x5c /* Command/Indication transmit */ 105 #define SQR 0x60 /* S/Q channel receive register */ 106 #define SQX 0x64 /* S/Q channel transmit register */ 107 #define PCTL 0x68 /* Peripheral control register */ 108 #define MOR 0x6c /* Monitor receive channel */ 109 #define MOX 0x70 /* Monitor transmit channel */ 110 #define MOSR 0x74 /* Monitor channel status register */ 111 #define MOCR 0x78 /* Monitor channel control register */ 112 #define GCR 0x7c /* GCI mode control register */ 113 #define XADDR 0xf4 /* Peripheral address register */ 114 #define XDATA 0xf8 /* Peripheral data register */ 115 #define EPCTL 0xfc /* Serial EEPROM control */ 116 117 /*---------------------------------------------------------------------------* 118 * register bits 119 *---------------------------------------------------------------------------*/ 120 #define D_CMDR_RACK 0x80 121 #define D_CMDR_RRST 0x40 122 #define D_CMDR_STT 0x10 123 #define D_CMDR_XMS 0x08 124 #define D_CMDR_XME 0x02 125 #define D_CMDR_XRST 0x01 126 127 #define D_MODE_MMS 0x80 128 #define D_MODE_RACT 0x40 129 #define D_MODE_TMS 0x10 130 #define D_MODE_TEE 0x08 131 #define D_MODE_MFD 0x04 132 #define D_MODE_DLP 0x02 133 #define D_MODE_RLP 0x01 134 135 #define D_TIMR_CNT(i) (((i) >> 5) & 0x07) 136 #define D_TIMR_VAL(i) ((i) & 0x1f) 137 138 #define ISTA_D_RMR 0x80 139 #define ISTA_D_RME 0x40 140 #define ISTA_D_XFR 0x20 141 #define ISTA_XINT1 0x10 142 #define ISTA_XINT0 0x08 143 #define ISTA_D_EXI 0x04 144 #define ISTA_B1_EXI 0x02 145 #define ISTA_B2_EXI 0x01 146 147 #define IMASK_D_RMR 0x80 148 #define IMASK_D_RME 0x40 149 #define IMASK_D_XFR 0x20 150 #define IMASK_XINT1 0x10 151 #define IMASK_XINT0 0x08 152 #define IMASK_D_EXI 0x04 153 #define IMASK_B1_EXI 0x02 154 #define IMASK_B2_EXI 0x01 155 156 #define D_EXIR_RDOV 0x80 157 #define D_EXIR_XDUN 0x40 158 #define D_EXIR_XCOL 0x20 159 #define D_EXIR_TIN2 0x10 160 #define D_EXIR_MOC 0x08 161 #define D_EXIR_ISC 0x04 162 #define D_EXIR_TEXP 0x02 163 #define D_EXIR_WEXP 0x01 164 165 #define D_EXIM_RDOV 0x80 166 #define D_EXIM_XDUN 0x40 167 #define D_EXIM_XCOL 0x20 168 #define D_EXIM_TIM2 0x10 169 #define D_EXIM_MOC 0x08 170 #define D_EXIM_ISC 0x04 171 #define D_EXIM_TEXP 0x02 172 #define D_EXIM_WEXP 0x01 173 174 #define D_STAR_XDOW 0x80 175 #define D_STAR_XBZ 0x20 176 #define D_STAR_DRDY 0x10 177 178 #define D_RSTA_RDOV 0x40 179 #define D_RSTA_CRCE 0x20 180 #define D_RSTA_RMB 0x10 181 182 #define D_RBCH_VN(i) (((i) >> 6) & 0x03) 183 #define D_RBCH_LOV 0x20 184 #define D_RBC(h,l) (((((h) & 0x1f)) << 8) + (l)) 185 186 #define D_TIMR2_TMD 0x80 187 #define D_TIMR2_TBCN(i) ((i) & 0x3f) 188 189 #define L1_RC_RC(i) ((i) & 0x0f) 190 191 #define D_CTL_WTT(i) (((i) > 6) & 0x03) 192 #define D_CTL_SRST 0x20 193 #define D_CTL_TPS 0x04 194 #define D_CTL_OPS(i) ((i) & 0x03) 195 196 #define CIR_SCC 0x80 197 #define CIR_ICC 0x40 198 #define CIR_CODR(i) ((i) & 0x0f) 199 200 #define CIX_ECK 0x00 201 #define CIX_RST 0x01 202 #define CIX_SCP 0x04 203 #define CIX_SSP 0x02 204 #define CIX_AR8 0x08 205 #define CIX_AR10 0x09 206 #define CIX_EAL 0x0a 207 #define CIX_DRC 0x0f 208 209 #define CIR_CE 0x07 210 #define CIR_DRD 0x00 211 #define CIR_LD 0x04 212 #define CIR_ARD 0x08 213 #define CIR_TI 0x0a 214 #define CIR_ATI 0x0b 215 #define CIR_AI8 0x0c 216 #define CIR_AI10 0x0d 217 #define CIR_CD 0x0f 218 219 #define SQR_XIND1 0x80 220 #define SQR_XIND0 0x40 221 #define SQR_MSYN 0x20 222 #define SQR_SCIE 0x10 223 #define SQR_S(i) ((i) & 0x0f) 224 225 #define SQX_SCIE 0x10 226 #define SQX_Q(i) ((i) & 0x0f) 227 228 229 #define B_CMDR_RACK 0x80 230 #define B_CMDR_RRST 0x40 231 #define B_CMDR_RACT 0x20 232 #define B_CMDR_XMS 0x04 233 #define B_CMDR_XME 0x02 234 #define B_CMDR_XRST 0x01 235 236 #define B_MODE_MMS 0x80 237 #define B_MODE_ITF 0x40 238 #define B_MODE_EPCM 0x20 239 #define B_MODE_BSW1 0x10 240 #define B_MODE_BSW0 0x08 241 #define B_MODE_SW56 0x04 242 #define B_MODE_FTS1 0x02 243 #define B_MODE_FTS0 0x01 244 245 #define B_EXIR_RMR 0x40 246 #define B_EXIR_RME 0x20 247 #define B_EXIR_RDOV 0x10 248 #define B_EXIR_XFR 0x02 249 #define B_EXIR_XDUN 0x01 250 251 #define B_EXIM_RMR 0x40 252 #define B_EXIM_RME 0x20 253 #define B_EXIM_RDOV 0x10 254 #define B_EXIM_XFR 0x02 255 #define B_EXIM_XDUN 0x01 256 257 #define B_STAR_RDOV 0x40 258 #define B_STAR_CRCE 0x20 259 #define B_STAR_RMB 0x10 260 #define B_STAR_XDOW 0x04 261 #define B_STAR_XBZ 0x01 262 263 #define B_RBC(h,l) (((((h) & 0x1f)) << 8) + (l)) 264 265 #endif /* !_IWICREG_H_ */ 266