1 /* $OpenBSD: mpt_mpilib.h,v 1.1 2004/03/06 03:03:07 krw Exp $ */ 2 /* $NetBSD: mpt_mpilib.h,v 1.2 2003/04/16 23:24:01 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 2000, 2001 by LSI Logic Corporation 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice immediately at the beginning of the file, without modification, 12 * this list of conditions, and the following disclaimer. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * 29 * Name: MPI_TYPE.H 30 * Title: MPI Basic type definitions 31 * Creation Date: June 6, 2000 32 * 33 * MPI Version: 01.02.01 34 * 35 * Version History 36 * --------------- 37 * 38 * Date Version Description 39 * -------- -------- ------------------------------------------------------ 40 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 41 * 06-06-00 01.00.01 Update version number for 1.0 release. 42 * 11-02-00 01.01.01 Original release for post 1.0 work 43 * 02-20-01 01.01.02 Added define and ifdef for MPI_POINTER. 44 * 08-08-01 01.02.01 Original release for v1.2 work. 45 * -------------------------------------------------------------------------- 46 */ 47 48 #ifndef MPI_TYPE_H 49 #define MPI_TYPE_H 50 51 52 /******************************************************************************* 53 * Define MPI_POINTER if it hasn't already been defined. By default MPI_POINTER 54 * is defined to be a near pointer. MPI_POINTER can be defined as a far pointer 55 * by defining MPI_POINTER as "far *" before this header file is included. 56 */ 57 #ifndef MPI_POINTER 58 #define MPI_POINTER * 59 #endif 60 61 62 /***************************************************************************** 63 * 64 * B a s i c T y p e s 65 * 66 *****************************************************************************/ 67 68 #ifdef __NetBSD__ 69 typedef int8_t S8; 70 typedef uint8_t U8; 71 typedef int16_t S16; 72 typedef uint16_t U16; 73 typedef int32_t S32; 74 typedef uint32_t U32; 75 #else /* ! __NetBSD__ */ 76 typedef signed char S8; 77 typedef unsigned char U8; 78 typedef signed short S16; 79 typedef unsigned short U16; 80 81 #if defined(unix) || defined(__arm) || defined(ALPHA) || defined(__GNUC__) 82 83 typedef signed int S32; 84 typedef unsigned int U32; 85 86 #else 87 88 typedef signed long S32; 89 typedef unsigned long U32; 90 91 #endif 92 #endif /* __NetBSD__ */ 93 94 95 typedef struct _S64 96 { 97 U32 Low; 98 S32 High; 99 } S64; 100 101 typedef struct _U64 102 { 103 U32 Low; 104 U32 High; 105 } U64; 106 107 108 /****************************************************************************/ 109 /* Pointers */ 110 /****************************************************************************/ 111 112 typedef S8 *PS8; 113 typedef U8 *PU8; 114 typedef S16 *PS16; 115 typedef U16 *PU16; 116 typedef S32 *PS32; 117 typedef U32 *PU32; 118 typedef S64 *PS64; 119 typedef U64 *PU64; 120 121 122 #endif 123 124 125 /* 126 * Copyright (c) 2000, 2001 by LSI Logic Corporation 127 * 128 * Redistribution and use in source and binary forms, with or without 129 * modification, are permitted provided that the following conditions 130 * are met: 131 * 1. Redistributions of source code must retain the above copyright 132 * notice immediately at the beginning of the file, without modification, 133 * this list of conditions, and the following disclaimer. 134 * 2. The name of the author may not be used to endorse or promote products 135 * derived from this software without specific prior written permission. 136 * 137 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 138 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 139 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 140 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 141 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 142 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 143 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 144 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 145 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 146 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 147 * SUCH DAMAGE. 148 * 149 * 150 * Name: MPI.H 151 * Title: MPI Message independent structures and definitions 152 * Creation Date: July 27, 2000 153 * 154 * MPI Version: 01.02.03 155 * 156 * Version History 157 * --------------- 158 * 159 * Date Version Description 160 * -------- -------- ------------------------------------------------------ 161 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 162 * 05-24-00 00.10.02 Added MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH definition. 163 * 06-06-00 01.00.01 Update MPI_VERSION_MAJOR and MPI_VERSION_MINOR. 164 * 06-22-00 01.00.02 Added MPI_IOCSTATUS_LAN_ definitions. 165 * Removed LAN_SUSPEND function definition. 166 * Added MPI_MSGFLAGS_CONTINUATION_REPLY definition. 167 * 06-30-00 01.00.03 Added MPI_CONTEXT_REPLY_TYPE_LAN definition. 168 * Added MPI_GET/SET_CONTEXT_REPLY_TYPE macros. 169 * 07-27-00 01.00.04 Added MPI_FAULT_ definitions. 170 * Removed MPI_IOCSTATUS_MSG/DATA_XFER_ERROR definitions. 171 * Added MPI_IOCSTATUS_INTERNAL_ERROR definition. 172 * Added MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH. 173 * 11-02-00 01.01.01 Original release for post 1.0 work. 174 * 12-04-00 01.01.02 Added new function codes. 175 * 01-09-01 01.01.03 Added more definitions to the system interface section 176 * Added MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT. 177 * 01-25-01 01.01.04 Changed MPI_VERSION_MINOR from 0x00 to 0x01. 178 * 02-20-01 01.01.05 Started using MPI_POINTER. 179 * Fixed value for MPI_DIAG_RW_ENABLE. 180 * Added defines for MPI_DIAG_PREVENT_IOC_BOOT and 181 * MPI_DIAG_CLEAR_FLASH_BAD_SIG. 182 * Obsoleted MPI_IOCSTATUS_TARGET_FC_ defines. 183 * 02-27-01 01.01.06 Removed MPI_HOST_INDEX_REGISTER define. 184 * Added function codes for RAID. 185 * 04-09-01 01.01.07 Added alternate define for MPI_DOORBELL_ACTIVE, 186 * MPI_DOORBELL_USED, to better match the spec. 187 * 08-08-01 01.02.01 Original release for v1.2 work. 188 * Changed MPI_VERSION_MINOR from 0x01 to 0x02. 189 * Added define MPI_FUNCTION_TOOLBOX. 190 * 09-28-01 01.02.02 New function code MPI_SCSI_ENCLOSURE_PROCESSOR. 191 * 11-01-01 01.02.03 Changed name to MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR. 192 * -------------------------------------------------------------------------- 193 */ 194 195 #ifndef MPI_H 196 #define MPI_H 197 198 199 /***************************************************************************** 200 * 201 * M P I V e r s i o n D e f i n i t i o n s 202 * 203 *****************************************************************************/ 204 205 #define MPI_VERSION_MAJOR (0x01) 206 #define MPI_VERSION_MINOR (0x02) 207 #define MPI_VERSION ((MPI_VERSION_MAJOR << 8) | MPI_VERSION_MINOR) 208 209 /* Note: The major versions of 0xe0 through 0xff are reserved */ 210 211 /***************************************************************************** 212 * 213 * I O C S t a t e D e f i n i t i o n s 214 * 215 *****************************************************************************/ 216 217 #define MPI_IOC_STATE_RESET (0x00000000) 218 #define MPI_IOC_STATE_READY (0x10000000) 219 #define MPI_IOC_STATE_OPERATIONAL (0x20000000) 220 #define MPI_IOC_STATE_FAULT (0x40000000) 221 222 #define MPI_IOC_STATE_MASK (0xF0000000) 223 #define MPI_IOC_STATE_SHIFT (28) 224 225 /* Fault state codes (product independent range 0x8000-0xFFFF) */ 226 227 #define MPI_FAULT_REQUEST_MESSAGE_PCI_PARITY_ERROR (0x8111) 228 #define MPI_FAULT_REQUEST_MESSAGE_PCI_BUS_FAULT (0x8112) 229 #define MPI_FAULT_REPLY_MESSAGE_PCI_PARITY_ERROR (0x8113) 230 #define MPI_FAULT_REPLY_MESSAGE_PCI_BUS_FAULT (0x8114) 231 #define MPI_FAULT_DATA_SEND_PCI_PARITY_ERROR (0x8115) 232 #define MPI_FAULT_DATA_SEND_PCI_BUS_FAULT (0x8116) 233 #define MPI_FAULT_DATA_RECEIVE_PCI_PARITY_ERROR (0x8117) 234 #define MPI_FAULT_DATA_RECEIVE_PCI_BUS_FAULT (0x8118) 235 236 237 /***************************************************************************** 238 * 239 * P C I S y s t e m I n t e r f a c e R e g i s t e r s 240 * 241 *****************************************************************************/ 242 243 /* S y s t e m D o o r b e l l */ 244 #define MPI_DOORBELL_OFFSET (0x00000000) 245 #define MPI_DOORBELL_ACTIVE (0x08000000) /* DoorbellUsed */ 246 #define MPI_DOORBELL_USED (MPI_DOORBELL_ACTIVE) 247 #define MPI_DOORBELL_ACTIVE_SHIFT (27) 248 #define MPI_DOORBELL_WHO_INIT_MASK (0x07000000) 249 #define MPI_DOORBELL_WHO_INIT_SHIFT (24) 250 #define MPI_DOORBELL_FUNCTION_MASK (0xFF000000) 251 #define MPI_DOORBELL_FUNCTION_SHIFT (24) 252 #define MPI_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 253 #define MPI_DOORBELL_ADD_DWORDS_SHIFT (16) 254 #define MPI_DOORBELL_DATA_MASK (0x0000FFFF) 255 256 257 #define MPI_WRITE_SEQUENCE_OFFSET (0x00000004) 258 #define MPI_WRSEQ_KEY_VALUE_MASK (0x0000000F) 259 #define MPI_WRSEQ_1ST_KEY_VALUE (0x04) 260 #define MPI_WRSEQ_2ND_KEY_VALUE (0x0B) 261 #define MPI_WRSEQ_3RD_KEY_VALUE (0x02) 262 #define MPI_WRSEQ_4TH_KEY_VALUE (0x07) 263 #define MPI_WRSEQ_5TH_KEY_VALUE (0x0D) 264 265 #define MPI_DIAGNOSTIC_OFFSET (0x00000008) 266 #define MPI_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 267 #define MPI_DIAG_PREVENT_IOC_BOOT (0x00000200) 268 #define MPI_DIAG_DRWE (0x00000080) 269 #define MPI_DIAG_FLASH_BAD_SIG (0x00000040) 270 #define MPI_DIAG_RESET_HISTORY (0x00000020) 271 #define MPI_DIAG_RW_ENABLE (0x00000010) 272 #define MPI_DIAG_RESET_ADAPTER (0x00000004) 273 #define MPI_DIAG_DISABLE_ARM (0x00000002) 274 #define MPI_DIAG_MEM_ENABLE (0x00000001) 275 276 #define MPI_TEST_BASE_ADDRESS_OFFSET (0x0000000C) 277 278 #define MPI_DIAG_RW_DATA_OFFSET (0x00000010) 279 280 #define MPI_DIAG_RW_ADDRESS_OFFSET (0x00000014) 281 282 #define MPI_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 283 #define MPI_HIS_IOP_DOORBELL_STATUS (0x80000000) 284 #define MPI_HIS_REPLY_MESSAGE_INTERRUPT (0x00000008) 285 #define MPI_HIS_DOORBELL_INTERRUPT (0x00000001) 286 287 #define MPI_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 288 #define MPI_HIM_RIM (0x00000008) 289 #define MPI_HIM_DIM (0x00000001) 290 291 #define MPI_REQUEST_QUEUE_OFFSET (0x00000040) 292 #define MPI_REQUEST_POST_FIFO_OFFSET (0x00000040) 293 294 #define MPI_REPLY_QUEUE_OFFSET (0x00000044) 295 #define MPI_REPLY_POST_FIFO_OFFSET (0x00000044) 296 #define MPI_REPLY_FREE_FIFO_OFFSET (0x00000044) 297 298 299 300 /***************************************************************************** 301 * 302 * M e s s a g e F r a m e D e s c r i p t o r s 303 * 304 *****************************************************************************/ 305 306 #define MPI_REQ_MF_DESCRIPTOR_NB_MASK (0x00000003) 307 #define MPI_REQ_MF_DESCRIPTOR_F_BIT (0x00000004) 308 #define MPI_REQ_MF_DESCRIPTOR_ADDRESS_MASK (0xFFFFFFF8) 309 310 #define MPI_ADDRESS_REPLY_A_BIT (0x80000000) 311 #define MPI_ADDRESS_REPLY_ADDRESS_MASK (0x7FFFFFFF) 312 313 #define MPI_CONTEXT_REPLY_A_BIT (0x80000000) 314 #define MPI_CONTEXT_REPLY_TYPE_MASK (0x60000000) 315 #define MPI_CONTEXT_REPLY_TYPE_SCSI_INIT (0x00) 316 #define MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET (0x01) 317 #define MPI_CONTEXT_REPLY_TYPE_LAN (0x02) 318 #define MPI_CONTEXT_REPLY_TYPE_SHIFT (29) 319 #define MPI_CONTEXT_REPLY_CONTEXT_MASK (0x1FFFFFFF) 320 321 322 /****************************************************************************/ 323 /* Context Reply macros */ 324 /****************************************************************************/ 325 326 #define MPI_GET_CONTEXT_REPLY_TYPE(x) (((x) & MPI_CONTEXT_REPLY_TYPE_MASK) \ 327 >> MPI_CONTEXT_REPLY_TYPE_SHIFT) 328 329 #define MPI_SET_CONTEXT_REPLY_TYPE(x, typ) \ 330 ((x) = ((x) & ~MPI_CONTEXT_REPLY_TYPE_MASK) | \ 331 (((typ) << MPI_CONTEXT_REPLY_TYPE_SHIFT) & \ 332 MPI_CONTEXT_REPLY_TYPE_MASK)) 333 334 335 /***************************************************************************** 336 * 337 * M e s s a g e F u n c t i o n s 338 * 0x80 -> 0x8F reserved for private message use per product 339 * 340 * 341 *****************************************************************************/ 342 343 #define MPI_FUNCTION_SCSI_IO_REQUEST (0x00) 344 #define MPI_FUNCTION_SCSI_TASK_MGMT (0x01) 345 #define MPI_FUNCTION_IOC_INIT (0x02) 346 #define MPI_FUNCTION_IOC_FACTS (0x03) 347 #define MPI_FUNCTION_CONFIG (0x04) 348 #define MPI_FUNCTION_PORT_FACTS (0x05) 349 #define MPI_FUNCTION_PORT_ENABLE (0x06) 350 #define MPI_FUNCTION_EVENT_NOTIFICATION (0x07) 351 #define MPI_FUNCTION_EVENT_ACK (0x08) 352 #define MPI_FUNCTION_FW_DOWNLOAD (0x09) 353 #define MPI_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A) 354 #define MPI_FUNCTION_TARGET_ASSIST (0x0B) 355 #define MPI_FUNCTION_TARGET_STATUS_SEND (0x0C) 356 #define MPI_FUNCTION_TARGET_MODE_ABORT (0x0D) 357 #define MPI_FUNCTION_TARGET_FC_BUF_POST_LINK_SRVC (0x0E) /* obsolete name */ 358 #define MPI_FUNCTION_TARGET_FC_RSP_LINK_SRVC (0x0F) /* obsolete name */ 359 #define MPI_FUNCTION_TARGET_FC_EX_SEND_LINK_SRVC (0x10) /* obsolete name */ 360 #define MPI_FUNCTION_TARGET_FC_ABORT (0x11) /* obsolete name */ 361 #define MPI_FUNCTION_FC_LINK_SRVC_BUF_POST (0x0E) 362 #define MPI_FUNCTION_FC_LINK_SRVC_RSP (0x0F) 363 #define MPI_FUNCTION_FC_EX_LINK_SRVC_SEND (0x10) 364 #define MPI_FUNCTION_FC_ABORT (0x11) 365 #define MPI_FUNCTION_FW_UPLOAD (0x12) 366 #define MPI_FUNCTION_FC_COMMON_TRANSPORT_SEND (0x13) 367 #define MPI_FUNCTION_FC_PRIMITIVE_SEND (0x14) 368 369 #define MPI_FUNCTION_RAID_ACTION (0x15) 370 #define MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 371 372 #define MPI_FUNCTION_TOOLBOX (0x17) 373 374 #define MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 375 376 #define MPI_FUNCTION_LAN_SEND (0x20) 377 #define MPI_FUNCTION_LAN_RECEIVE (0x21) 378 #define MPI_FUNCTION_LAN_RESET (0x22) 379 380 #define MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 381 #define MPI_FUNCTION_IO_UNIT_RESET (0x41) 382 #define MPI_FUNCTION_HANDSHAKE (0x42) 383 #define MPI_FUNCTION_REPLY_FRAME_REMOVAL (0x43) 384 385 386 387 /***************************************************************************** 388 * 389 * S c a t t e r G a t h e r E l e m e n t s 390 * 391 *****************************************************************************/ 392 393 /****************************************************************************/ 394 /* Simple element structures */ 395 /****************************************************************************/ 396 397 typedef struct _SGE_SIMPLE32 398 { 399 U32 FlagsLength; 400 U32 Address; 401 } SGE_SIMPLE32, MPI_POINTER PTR_SGE_SIMPLE32, 402 SGESimple32_t, MPI_POINTER pSGESimple32_t; 403 404 typedef struct _SGE_SIMPLE64 405 { 406 U32 FlagsLength; 407 U64 Address; 408 } SGE_SIMPLE64, MPI_POINTER PTR_SGE_SIMPLE64, 409 SGESimple64_t, MPI_POINTER pSGESimple64_t; 410 411 typedef struct _SGE_SIMPLE_UNION 412 { 413 U32 FlagsLength; 414 union 415 { 416 U32 Address32; 417 U64 Address64; 418 } _u; 419 } SGESimpleUnion_t, MPI_POINTER pSGESimpleUnion_t, 420 SGE_SIMPLE_UNION, MPI_POINTER PTR_SGE_SIMPLE_UNION; 421 422 /****************************************************************************/ 423 /* Chain element structures */ 424 /****************************************************************************/ 425 426 typedef struct _SGE_CHAIN32 427 { 428 U16 Length; 429 U8 NextChainOffset; 430 U8 Flags; 431 U32 Address; 432 } SGE_CHAIN32, MPI_POINTER PTR_SGE_CHAIN32, 433 SGEChain32_t, MPI_POINTER pSGEChain32_t; 434 435 typedef struct _SGE_CHAIN64 436 { 437 U16 Length; 438 U8 NextChainOffset; 439 U8 Flags; 440 U64 Address; 441 } SGE_CHAIN64, MPI_POINTER PTR_SGE_CHAIN64, 442 SGEChain64_t, MPI_POINTER pSGEChain64_t; 443 444 typedef struct _SGE_CHAIN_UNION 445 { 446 U16 Length; 447 U8 NextChainOffset; 448 U8 Flags; 449 union 450 { 451 U32 Address32; 452 U64 Address64; 453 } _u; 454 } SGE_CHAIN_UNION, MPI_POINTER PTR_SGE_CHAIN_UNION, 455 SGEChainUnion_t, MPI_POINTER pSGEChainUnion_t; 456 457 /****************************************************************************/ 458 /* Transaction Context element */ 459 /****************************************************************************/ 460 461 typedef struct _SGE_TRANSACTION32 462 { 463 U8 Reserved; 464 U8 ContextSize; 465 U8 DetailsLength; 466 U8 Flags; 467 U32 TransactionContext[1]; 468 U32 TransactionDetails[1]; 469 } SGE_TRANSACTION32, MPI_POINTER PTR_SGE_TRANSACTION32, 470 SGETransaction32_t, MPI_POINTER pSGETransaction32_t; 471 472 typedef struct _SGE_TRANSACTION64 473 { 474 U8 Reserved; 475 U8 ContextSize; 476 U8 DetailsLength; 477 U8 Flags; 478 U32 TransactionContext[2]; 479 U32 TransactionDetails[1]; 480 } SGE_TRANSACTION64, MPI_POINTER PTR_SGE_TRANSACTION64, 481 SGETransaction64_t, MPI_POINTER pSGETransaction64_t; 482 483 typedef struct _SGE_TRANSACTION96 484 { 485 U8 Reserved; 486 U8 ContextSize; 487 U8 DetailsLength; 488 U8 Flags; 489 U32 TransactionContext[3]; 490 U32 TransactionDetails[1]; 491 } SGE_TRANSACTION96, MPI_POINTER PTR_SGE_TRANSACTION96, 492 SGETransaction96_t, MPI_POINTER pSGETransaction96_t; 493 494 typedef struct _SGE_TRANSACTION128 495 { 496 U8 Reserved; 497 U8 ContextSize; 498 U8 DetailsLength; 499 U8 Flags; 500 U32 TransactionContext[4]; 501 U32 TransactionDetails[1]; 502 } SGE_TRANSACTION128, MPI_POINTER PTR_SGE_TRANSACTION128, 503 SGETransaction_t128, MPI_POINTER pSGETransaction_t128; 504 505 typedef struct _SGE_TRANSACTION_UNION 506 { 507 U8 Reserved; 508 U8 ContextSize; 509 U8 DetailsLength; 510 U8 Flags; 511 union 512 { 513 U32 TransactionContext32[1]; 514 U32 TransactionContext64[2]; 515 U32 TransactionContext96[3]; 516 U32 TransactionContext128[4]; 517 } _u; 518 U32 TransactionDetails[1]; 519 } SGE_TRANSACTION_UNION, MPI_POINTER PTR_SGE_TRANSACTION_UNION, 520 SGETransactionUnion_t, MPI_POINTER pSGETransactionUnion_t; 521 522 523 /****************************************************************************/ 524 /* SGE IO types union for IO SGL's */ 525 /****************************************************************************/ 526 527 typedef struct _SGE_IO_UNION 528 { 529 union 530 { 531 SGE_SIMPLE_UNION Simple; 532 SGE_CHAIN_UNION Chain; 533 } _u; 534 } SGE_IO_UNION, MPI_POINTER PTR_SGE_IO_UNION, 535 SGEIOUnion_t, MPI_POINTER pSGEIOUnion_t; 536 537 /****************************************************************************/ 538 /* SGE union for SGL's with Simple and Transaction elements */ 539 /****************************************************************************/ 540 541 typedef struct _SGE_TRANS_SIMPLE_UNION 542 { 543 union 544 { 545 SGE_SIMPLE_UNION Simple; 546 SGE_TRANSACTION_UNION Transaction; 547 } _u; 548 } SGE_TRANS_SIMPLE_UNION, MPI_POINTER PTR_SGE_TRANS_SIMPLE_UNION, 549 SGETransSimpleUnion_t, MPI_POINTER pSGETransSimpleUnion_t; 550 551 /****************************************************************************/ 552 /* All SGE types union */ 553 /****************************************************************************/ 554 555 typedef struct _SGE_MPI_UNION 556 { 557 union 558 { 559 SGE_SIMPLE_UNION Simple; 560 SGE_CHAIN_UNION Chain; 561 SGE_TRANSACTION_UNION Transaction; 562 } _u; 563 } SGE_MPI_UNION, MPI_POINTER PTR_SGE_MPI_UNION, 564 MPI_SGE_UNION_t, MPI_POINTER pMPI_SGE_UNION_t, 565 SGEAllUnion_t, MPI_POINTER pSGEAllUnion_t; 566 567 568 /****************************************************************************/ 569 /* SGE field definition and masks */ 570 /****************************************************************************/ 571 572 /* Flags field bit definitions */ 573 574 #define MPI_SGE_FLAGS_LAST_ELEMENT (0x80) 575 #define MPI_SGE_FLAGS_END_OF_BUFFER (0x40) 576 #define MPI_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 577 #define MPI_SGE_FLAGS_LOCAL_ADDRESS (0x08) 578 #define MPI_SGE_FLAGS_DIRECTION (0x04) 579 #define MPI_SGE_FLAGS_ADDRESS_SIZE (0x02) 580 #define MPI_SGE_FLAGS_END_OF_LIST (0x01) 581 582 #define MPI_SGE_FLAGS_SHIFT (24) 583 584 #define MPI_SGE_LENGTH_MASK (0x00FFFFFF) 585 #define MPI_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 586 587 /* Element Type */ 588 589 #define MPI_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 590 #define MPI_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 591 #define MPI_SGE_FLAGS_CHAIN_ELEMENT (0x30) 592 #define MPI_SGE_FLAGS_ELEMENT_MASK (0x30) 593 594 /* Address location */ 595 596 #define MPI_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 597 598 /* Direction */ 599 600 #define MPI_SGE_FLAGS_IOC_TO_HOST (0x00) 601 #define MPI_SGE_FLAGS_HOST_TO_IOC (0x04) 602 603 /* Address Size */ 604 605 #define MPI_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 606 #define MPI_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 607 608 /* Context Size */ 609 610 #define MPI_SGE_FLAGS_32_BIT_CONTEXT (0x00) 611 #define MPI_SGE_FLAGS_64_BIT_CONTEXT (0x02) 612 #define MPI_SGE_FLAGS_96_BIT_CONTEXT (0x04) 613 #define MPI_SGE_FLAGS_128_BIT_CONTEXT (0x06) 614 615 #define MPI_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 616 #define MPI_SGE_CHAIN_OFFSET_SHIFT (16) 617 618 619 /****************************************************************************/ 620 /* SGE operation Macros */ 621 /****************************************************************************/ 622 623 /* SIMPLE FlagsLength manipulations... */ 624 #define MPI_SGE_SET_FLAGS(f) ((U32)(f) << MPI_SGE_FLAGS_SHIFT) 625 #define MPI_SGE_GET_FLAGS(fl) (((fl) & ~MPI_SGE_LENGTH_MASK) >> MPI_SGE_FLAGS_SHIFT) 626 #define MPI_SGE_LENGTH(fl) ((fl) & MPI_SGE_LENGTH_MASK) 627 #define MPI_SGE_CHAIN_LENGTH(fl) ((fl) & MPI_SGE_CHAIN_LENGTH_MASK) 628 629 #define MPI_SGE_SET_FLAGS_LENGTH(f,l) (MPI_SGE_SET_FLAGS(f) | MPI_SGE_LENGTH(l)) 630 631 #define MPI_pSGE_GET_FLAGS(psg) MPI_SGE_GET_FLAGS((psg)->FlagsLength) 632 #define MPI_pSGE_GET_LENGTH(psg) MPI_SGE_LENGTH((psg)->FlagsLength) 633 #define MPI_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI_SGE_SET_FLAGS_LENGTH(f,l) 634 /* CAUTION - The following are READ-MODIFY-WRITE! */ 635 #define MPI_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI_SGE_SET_FLAGS(f) 636 #define MPI_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI_SGE_LENGTH(l) 637 638 #define MPI_GET_CHAIN_OFFSET(x) ((x&MPI_SGE_CHAIN_OFFSET_MASK)>>MPI_SGE_CHAIN_OFFSET_SHIFT) 639 640 641 642 /***************************************************************************** 643 * 644 * S t a n d a r d M e s s a g e S t r u c t u r e s 645 * 646 *****************************************************************************/ 647 648 /****************************************************************************/ 649 /* Standard message request header for all request messages */ 650 /****************************************************************************/ 651 652 typedef struct _MSG_REQUEST_HEADER 653 { 654 U8 Reserved[2]; /* function specific */ 655 U8 ChainOffset; 656 U8 Function; 657 U8 Reserved1[3]; /* function specific */ 658 U8 MsgFlags; 659 U32 MsgContext; 660 } MSG_REQUEST_HEADER, MPI_POINTER PTR_MSG_REQUEST_HEADER, 661 MPIHeader_t, MPI_POINTER pMPIHeader_t; 662 663 664 /****************************************************************************/ 665 /* Default Reply */ 666 /****************************************************************************/ 667 668 typedef struct _MSG_DEFAULT_REPLY 669 { 670 U8 Reserved[2]; /* function specific */ 671 U8 MsgLength; 672 U8 Function; 673 U8 Reserved1[3]; /* function specific */ 674 U8 MsgFlags; 675 U32 MsgContext; 676 U8 Reserved2[2]; /* function specific */ 677 U16 IOCStatus; 678 U32 IOCLogInfo; 679 } MSG_DEFAULT_REPLY, MPI_POINTER PTR_MSG_DEFAULT_REPLY, 680 MPIDefaultReply_t, MPI_POINTER pMPIDefaultReply_t; 681 682 683 /* MsgFlags definition for all replies */ 684 685 #define MPI_MSGFLAGS_CONTINUATION_REPLY (0x80) 686 687 688 /***************************************************************************** 689 * 690 * I O C S t a t u s V a l u e s 691 * 692 *****************************************************************************/ 693 694 /****************************************************************************/ 695 /* Common IOCStatus values for all replies */ 696 /****************************************************************************/ 697 698 #define MPI_IOCSTATUS_SUCCESS (0x0000) 699 #define MPI_IOCSTATUS_INVALID_FUNCTION (0x0001) 700 #define MPI_IOCSTATUS_BUSY (0x0002) 701 #define MPI_IOCSTATUS_INVALID_SGL (0x0003) 702 #define MPI_IOCSTATUS_INTERNAL_ERROR (0x0004) 703 #define MPI_IOCSTATUS_RESERVED (0x0005) 704 #define MPI_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 705 #define MPI_IOCSTATUS_INVALID_FIELD (0x0007) 706 #define MPI_IOCSTATUS_INVALID_STATE (0x0008) 707 708 /****************************************************************************/ 709 /* Config IOCStatus values */ 710 /****************************************************************************/ 711 712 #define MPI_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 713 #define MPI_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 714 #define MPI_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 715 #define MPI_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 716 #define MPI_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 717 #define MPI_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 718 719 /****************************************************************************/ 720 /* SCSIIO Reply (SPI & FCP) initiator values */ 721 /****************************************************************************/ 722 723 #define MPI_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 724 #define MPI_IOCSTATUS_SCSI_INVALID_BUS (0x0041) 725 #define MPI_IOCSTATUS_SCSI_INVALID_TARGETID (0x0042) 726 #define MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 727 #define MPI_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 728 #define MPI_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 729 #define MPI_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 730 #define MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 731 #define MPI_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 732 #define MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 733 #define MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 734 #define MPI_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 735 #define MPI_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 736 737 /****************************************************************************/ 738 /* SCSI (SPI & FCP) target values */ 739 /****************************************************************************/ 740 741 #define MPI_IOCSTATUS_TARGET_PRIORITY_IO (0x0060) 742 #define MPI_IOCSTATUS_TARGET_INVALID_PORT (0x0061) 743 #define MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX (0x0062) 744 #define MPI_IOCSTATUS_TARGET_ABORTED (0x0063) 745 #define MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 746 #define MPI_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 747 #define MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 748 #define MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT (0x006B) 749 750 /****************************************************************************/ 751 /* Additional FCP target values */ 752 /****************************************************************************/ 753 754 #define MPI_IOCSTATUS_TARGET_FC_ABORTED (0x0066) /* obsolete */ 755 #define MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID (0x0067) /* obsolete */ 756 #define MPI_IOCSTATUS_TARGET_FC_DID_INVALID (0x0068) /* obsolete */ 757 #define MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT (0x0069) /* obsolete */ 758 759 /****************************************************************************/ 760 /* Fibre Channel Direct Access values */ 761 /****************************************************************************/ 762 763 #define MPI_IOCSTATUS_FC_ABORTED (0x0066) 764 #define MPI_IOCSTATUS_FC_RX_ID_INVALID (0x0067) 765 #define MPI_IOCSTATUS_FC_DID_INVALID (0x0068) 766 #define MPI_IOCSTATUS_FC_NODE_LOGGED_OUT (0x0069) 767 768 /****************************************************************************/ 769 /* LAN values */ 770 /****************************************************************************/ 771 772 #define MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND (0x0080) 773 #define MPI_IOCSTATUS_LAN_DEVICE_FAILURE (0x0081) 774 #define MPI_IOCSTATUS_LAN_TRANSMIT_ERROR (0x0082) 775 #define MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED (0x0083) 776 #define MPI_IOCSTATUS_LAN_RECEIVE_ERROR (0x0084) 777 #define MPI_IOCSTATUS_LAN_RECEIVE_ABORTED (0x0085) 778 #define MPI_IOCSTATUS_LAN_PARTIAL_PACKET (0x0086) 779 #define MPI_IOCSTATUS_LAN_CANCELED (0x0087) 780 781 782 /****************************************************************************/ 783 /* IOCStatus flag to indicate that log info is available */ 784 /****************************************************************************/ 785 786 #define MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 787 #define MPI_IOCSTATUS_MASK (0x7FFF) 788 789 /****************************************************************************/ 790 /* LogInfo Types */ 791 /****************************************************************************/ 792 793 #define MPI_IOCLOGINFO_TYPE_MASK (0xF0000000) 794 #define MPI_IOCLOGINFO_TYPE_NONE (0x0) 795 #define MPI_IOCLOGINFO_TYPE_SCSI (0x1) 796 #define MPI_IOCLOGINFO_TYPE_FC (0x2) 797 #define MPI_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 798 799 800 #endif 801 802 /* 803 * Copyright (c) 2000, 2001 by LSI Logic Corporation 804 * 805 * Redistribution and use in source and binary forms, with or without 806 * modification, are permitted provided that the following conditions 807 * are met: 808 * 1. Redistributions of source code must retain the above copyright 809 * notice immediately at the beginning of the file, without modification, 810 * this list of conditions, and the following disclaimer. 811 * 2. The name of the author may not be used to endorse or promote products 812 * derived from this software without specific prior written permission. 813 * 814 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 815 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 816 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 817 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 818 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 819 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 820 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 821 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 822 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 823 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 824 * SUCH DAMAGE. 825 * 826 * 827 * Name: MPI_CNFG.H 828 * Title: MPI Config message, structures, and Pages 829 * Creation Date: July 27, 2000 830 * 831 * MPI Version: 01.02.05 832 * 833 * Version History 834 * --------------- 835 * 836 * Date Version Description 837 * -------- -------- ------------------------------------------------------ 838 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 839 * 06-06-00 01.00.01 Update version number for 1.0 release. 840 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 841 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 842 * fields to FC_DEVICE_0 page, updated the page version. 843 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 844 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 845 * and updated the page versions. 846 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 847 * page and updated the page version. 848 * Added Information field and _INFO_PARAMS_NEGOTIATED 849 * definitionto SCSI_DEVICE_0 page. 850 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 851 * page version. 852 * Added BucketsRemaining to LAN_1 page, redefined the 853 * state values, and updated the page version. 854 * Revised bus width definitions in SCSI_PORT_0, 855 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 856 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 857 * version. 858 * Moved FC_DEVICE_0 PageAddress description to spec. 859 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 860 * widths in IOC_0 page and updated the page version. 861 * 11-02-00 01.01.01 Original release for post 1.0 work 862 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 863 * Port Page 2, FC Port Page 4, FC Port Page 5 864 * 11-15-00 01.01.02 Interim changes to match proposals 865 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 866 * 12-05-00 01.01.04 Modified config page actions. 867 * 01-09-01 01.01.05 Added defines for page address formats. 868 * Data size for Manufacturing pages 2 and 3 no longer 869 * defined here. 870 * Io Unit Page 2 size is fixed at 4 adapters and some 871 * flags were changed. 872 * SCSI Port Page 2 Device Settings modified. 873 * New fields added to FC Port Page 0 and some flags 874 * cleaned up. 875 * Removed impedance flash from FC Port Page 1. 876 * Added FC Port pages 6 and 7. 877 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 878 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 879 * Added some LinkType defines for FcPortPage0. 880 * 02-20-01 01.01.08 Started using MPI_POINTER. 881 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 882 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 883 * Added definitions and structures for IOC Page 2 and 884 * RAID Volume Page 2. 885 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 886 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 887 * Added VendorId and ProductRevLevel fields to 888 * RAIDVOL2_IM_PHYS_ID struct. 889 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 890 * defines to make them compatible to MPI version 1.0. 891 * Added structure offset comments. 892 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 893 * removed some obsolete ones. 894 * Added IO Unit Page 3. 895 * Modified defines for Scsi Port Page 2. 896 * Modified RAID Volume Pages. 897 * 08-08-01 01.02.01 Original release for v1.2 work. 898 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 899 * Added defines for the SEP bits in RVP2 VolumeSettings. 900 * Modified the DeviceSettings field in RVP2 to use the 901 * proper structure. 902 * Added defines for SES, SAF-TE, and cross channel for 903 * IOCPage2 CapabilitiesFlags. 904 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 905 * Removed define for 906 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 907 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 908 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 909 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 910 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 911 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 912 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 913 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 914 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 915 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 916 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 917 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 918 * Added rejected bits to SCSI Device Page 0 Information. 919 * Increased size of ALPA array in FC Port Page 2 by one 920 * and removed a one byte reserved field. 921 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 922 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 923 * Added structures for Manufacturing Page 4, IO Unit 924 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 925 * RAID PhysDisk Page 0. 926 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 927 * Modified some of the new defines to make them 32 928 * character unique. 929 * Modified how variable length pages (arrays) are defined. 930 * Added generic defines for hot spare pools and RAID 931 * volume types. 932 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 933 * -------------------------------------------------------------------------- 934 */ 935 936 #ifndef MPI_CNFG_H 937 #define MPI_CNFG_H 938 939 940 /***************************************************************************** 941 * 942 * C o n f i g M e s s a g e a n d S t r u c t u r e s 943 * 944 *****************************************************************************/ 945 946 typedef struct _CONFIG_PAGE_HEADER 947 { 948 U8 PageVersion; /* 00h */ 949 U8 PageLength; /* 01h */ 950 U8 PageNumber; /* 02h */ 951 U8 PageType; /* 03h */ 952 } fCONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 953 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 954 955 typedef union _CONFIG_PAGE_HEADER_UNION 956 { 957 ConfigPageHeader_t Struct; 958 U8 Bytes[4]; 959 U16 Word16[2]; 960 U32 Word32; 961 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 962 fCONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 963 964 965 /**************************************************************************** 966 * PageType field values 967 ****************************************************************************/ 968 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 969 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 970 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 971 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 972 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 973 974 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 975 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 976 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 977 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 978 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 979 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 980 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 981 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 982 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 983 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 984 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 985 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 986 987 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 988 989 990 /**************************************************************************** 991 * PageAddress field values 992 ****************************************************************************/ 993 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 994 995 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 996 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 997 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 998 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 999 1000 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 1001 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 1002 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 1003 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 1004 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 1005 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 1006 1007 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 1008 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 1009 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 1010 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 1011 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 1012 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 1013 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 1014 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 1015 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 1016 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 1017 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 1018 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 1019 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 1020 1021 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 1022 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 1023 1024 1025 1026 /**************************************************************************** 1027 * Config Request Message 1028 ****************************************************************************/ 1029 typedef struct _MSG_CONFIG 1030 { 1031 U8 Action; /* 00h */ 1032 U8 Reserved; /* 01h */ 1033 U8 ChainOffset; /* 02h */ 1034 U8 Function; /* 03h */ 1035 U8 Reserved1[3]; /* 04h */ 1036 U8 MsgFlags; /* 07h */ 1037 U32 MsgContext; /* 08h */ 1038 U8 Reserved2[8]; /* 0Ch */ 1039 fCONFIG_PAGE_HEADER Header; /* 14h */ 1040 U32 PageAddress; /* 18h */ 1041 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 1042 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 1043 Config_t, MPI_POINTER pConfig_t; 1044 1045 1046 /**************************************************************************** 1047 * Action field values 1048 ****************************************************************************/ 1049 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 1050 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 1051 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 1052 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 1053 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 1054 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 1055 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 1056 1057 1058 /* Config Reply Message */ 1059 typedef struct _MSG_CONFIG_REPLY 1060 { 1061 U8 Action; /* 00h */ 1062 U8 Reserved; /* 01h */ 1063 U8 MsgLength; /* 02h */ 1064 U8 Function; /* 03h */ 1065 U8 Reserved1[3]; /* 04h */ 1066 U8 MsgFlags; /* 07h */ 1067 U32 MsgContext; /* 08h */ 1068 U8 Reserved2[2]; /* 0Ch */ 1069 U16 IOCStatus; /* 0Eh */ 1070 U32 IOCLogInfo; /* 10h */ 1071 fCONFIG_PAGE_HEADER Header; /* 14h */ 1072 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 1073 ConfigReply_t, MPI_POINTER pConfigReply_t; 1074 1075 1076 1077 /***************************************************************************** 1078 * 1079 * C o n f i g u r a t i o n P a g e s 1080 * 1081 *****************************************************************************/ 1082 1083 /**************************************************************************** 1084 * Manufacturing Config pages 1085 ****************************************************************************/ 1086 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 1087 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 1088 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 1089 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 1090 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 1091 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 1092 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 1093 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 1094 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 1095 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 1096 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 1097 1098 typedef struct _CONFIG_PAGE_MANUFACTURING_0 1099 { 1100 fCONFIG_PAGE_HEADER Header; /* 00h */ 1101 U8 ChipName[16]; /* 04h */ 1102 U8 ChipRevision[8]; /* 14h */ 1103 U8 BoardName[16]; /* 1Ch */ 1104 U8 BoardAssembly[16]; /* 2Ch */ 1105 U8 BoardTracerNumber[16]; /* 3Ch */ 1106 1107 } fCONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 1108 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 1109 1110 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 1111 1112 1113 typedef struct _CONFIG_PAGE_MANUFACTURING_1 1114 { 1115 fCONFIG_PAGE_HEADER Header; /* 00h */ 1116 U8 VPD[256]; /* 04h */ 1117 } fCONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 1118 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 1119 1120 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 1121 1122 1123 typedef struct _MPI_CHIP_REVISION_ID 1124 { 1125 U16 DeviceID; /* 00h */ 1126 U8 PCIRevisionID; /* 02h */ 1127 U8 Reserved; /* 03h */ 1128 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 1129 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 1130 1131 1132 /* 1133 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1134 * one and check Header.PageLength at runtime. 1135 */ 1136 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 1137 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 1138 #endif 1139 1140 typedef struct _CONFIG_PAGE_MANUFACTURING_2 1141 { 1142 fCONFIG_PAGE_HEADER Header; /* 00h */ 1143 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 1144 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 1145 } fCONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 1146 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 1147 1148 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 1149 1150 1151 /* 1152 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1153 * one and check Header.PageLength at runtime. 1154 */ 1155 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 1156 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 1157 #endif 1158 1159 typedef struct _CONFIG_PAGE_MANUFACTURING_3 1160 { 1161 fCONFIG_PAGE_HEADER Header; /* 00h */ 1162 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 1163 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 1164 } fCONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 1165 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 1166 1167 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 1168 1169 1170 typedef struct _CONFIG_PAGE_MANUFACTURING_4 1171 { 1172 fCONFIG_PAGE_HEADER Header; /* 00h */ 1173 U32 Reserved1; /* 04h */ 1174 U8 InfoOffset0; /* 08h */ 1175 U8 InfoSize0; /* 09h */ 1176 U8 InfoOffset1; /* 0Ah */ 1177 U8 InfoSize1; /* 0Bh */ 1178 U8 InquirySize; /* 0Ch */ 1179 U8 Reserved2; /* 0Dh */ 1180 U16 Reserved3; /* 0Eh */ 1181 U8 InquiryData[56]; /* 10h */ 1182 U32 ISVolumeSettings; /* 48h */ 1183 U32 IMEVolumeSettings; /* 4Ch */ 1184 U32 IMVolumeSettings; /* 50h */ 1185 } fCONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 1186 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 1187 1188 #define MPI_MANUFACTURING4_PAGEVERSION (0x00) 1189 1190 1191 /**************************************************************************** 1192 * IO Unit Config Pages 1193 ****************************************************************************/ 1194 1195 typedef struct _CONFIG_PAGE_IO_UNIT_0 1196 { 1197 fCONFIG_PAGE_HEADER Header; /* 00h */ 1198 U64 UniqueValue; /* 04h */ 1199 } fCONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 1200 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 1201 1202 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 1203 1204 1205 typedef struct _CONFIG_PAGE_IO_UNIT_1 1206 { 1207 fCONFIG_PAGE_HEADER Header; /* 00h */ 1208 U32 Flags; /* 04h */ 1209 } fCONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 1210 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 1211 1212 #define MPI_IOUNITPAGE1_PAGEVERSION (0x00) 1213 1214 /* IO Unit Page 1 Flags defines */ 1215 1216 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 1217 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 1218 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 1219 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 1220 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 1221 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 1222 1223 1224 typedef struct _MPI_ADAPTER_INFO 1225 { 1226 U8 PciBusNumber; /* 00h */ 1227 U8 PciDeviceAndFunctionNumber; /* 01h */ 1228 U16 AdapterFlags; /* 02h */ 1229 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 1230 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 1231 1232 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1233 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1234 1235 typedef struct _CONFIG_PAGE_IO_UNIT_2 1236 { 1237 fCONFIG_PAGE_HEADER Header; /* 00h */ 1238 U32 Flags; /* 04h */ 1239 U32 BiosVersion; /* 08h */ 1240 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 1241 } fCONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 1242 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 1243 1244 #define MPI_IOUNITPAGE2_PAGEVERSION (0x00) 1245 1246 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 1247 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 1248 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 1249 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 1250 1251 1252 /* 1253 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1254 * one and check Header.PageLength at runtime. 1255 */ 1256 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 1257 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 1258 #endif 1259 1260 typedef struct _CONFIG_PAGE_IO_UNIT_3 1261 { 1262 fCONFIG_PAGE_HEADER Header; /* 00h */ 1263 U8 GPIOCount; /* 04h */ 1264 U8 Reserved1; /* 05h */ 1265 U16 Reserved2; /* 06h */ 1266 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 1267 } fCONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 1268 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 1269 1270 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 1271 1272 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 1273 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 1274 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 1275 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 1276 1277 1278 /**************************************************************************** 1279 * IOC Config Pages 1280 ****************************************************************************/ 1281 1282 typedef struct _CONFIG_PAGE_IOC_0 1283 { 1284 fCONFIG_PAGE_HEADER Header; /* 00h */ 1285 U32 TotalNVStore; /* 04h */ 1286 U32 FreeNVStore; /* 08h */ 1287 U16 VendorID; /* 0Ch */ 1288 U16 DeviceID; /* 0Eh */ 1289 U8 RevisionID; /* 10h */ 1290 U8 Reserved[3]; /* 11h */ 1291 U32 ClassCode; /* 14h */ 1292 U16 SubsystemVendorID; /* 18h */ 1293 U16 SubsystemID; /* 1Ah */ 1294 } fCONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 1295 IOCPage0_t, MPI_POINTER pIOCPage0_t; 1296 1297 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 1298 1299 1300 typedef struct _CONFIG_PAGE_IOC_1 1301 { 1302 fCONFIG_PAGE_HEADER Header; /* 00h */ 1303 U32 Flags; /* 04h */ 1304 U32 CoalescingTimeout; /* 08h */ 1305 U8 CoalescingDepth; /* 0Ch */ 1306 U8 Reserved[3]; /* 0Dh */ 1307 } fCONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 1308 IOCPage1_t, MPI_POINTER pIOCPage1_t; 1309 1310 #define MPI_IOCPAGE1_PAGEVERSION (0x00) 1311 1312 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 1313 1314 1315 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 1316 { 1317 U8 VolumeID; /* 00h */ 1318 U8 VolumeBus; /* 01h */ 1319 U8 VolumeIOC; /* 02h */ 1320 U8 VolumePageNumber; /* 03h */ 1321 U8 VolumeType; /* 04h */ 1322 U8 Reserved2; /* 05h */ 1323 U16 Reserved3; /* 06h */ 1324 } fCONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 1325 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 1326 1327 /* 1328 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1329 * one and check Header.PageLength at runtime. 1330 */ 1331 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 1332 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 1333 #endif 1334 1335 typedef struct _CONFIG_PAGE_IOC_2 1336 { 1337 fCONFIG_PAGE_HEADER Header; /* 00h */ 1338 U32 CapabilitiesFlags; /* 04h */ 1339 U8 NumActiveVolumes; /* 08h */ 1340 U8 MaxVolumes; /* 09h */ 1341 U8 NumActivePhysDisks; /* 0Ah */ 1342 U8 MaxPhysDisks; /* 0Bh */ 1343 fCONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 1344 } fCONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 1345 IOCPage2_t, MPI_POINTER pIOCPage2_t; 1346 1347 #define MPI_IOCPAGE2_PAGEVERSION (0x01) 1348 1349 /* IOC Page 2 Capabilities flags */ 1350 1351 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 1352 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 1353 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 1354 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 1355 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 1356 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 1357 1358 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 1359 1360 #define MPI_RAID_VOL_TYPE_IS (0x00) 1361 #define MPI_RAID_VOL_TYPE_IME (0x01) 1362 #define MPI_RAID_VOL_TYPE_IM (0x02) 1363 1364 1365 typedef struct _IOC_3_PHYS_DISK 1366 { 1367 U8 PhysDiskID; /* 00h */ 1368 U8 PhysDiskBus; /* 01h */ 1369 U8 PhysDiskIOC; /* 02h */ 1370 U8 PhysDiskNum; /* 03h */ 1371 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 1372 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 1373 1374 /* 1375 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1376 * one and check Header.PageLength at runtime. 1377 */ 1378 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 1379 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 1380 #endif 1381 1382 typedef struct _CONFIG_PAGE_IOC_3 1383 { 1384 fCONFIG_PAGE_HEADER Header; /* 00h */ 1385 U8 NumPhysDisks; /* 04h */ 1386 U8 Reserved1; /* 05h */ 1387 U16 Reserved2; /* 06h */ 1388 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 1389 } fCONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 1390 IOCPage3_t, MPI_POINTER pIOCPage3_t; 1391 1392 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 1393 1394 1395 typedef struct _IOC_4_SEP 1396 { 1397 U8 SEPTargetID; /* 00h */ 1398 U8 SEPBus; /* 01h */ 1399 U16 Reserved; /* 02h */ 1400 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 1401 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 1402 1403 /* 1404 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1405 * one and check Header.PageLength at runtime. 1406 */ 1407 #ifndef MPI_IOC_PAGE_4_SEP_MAX 1408 #define MPI_IOC_PAGE_4_SEP_MAX (1) 1409 #endif 1410 1411 typedef struct _CONFIG_PAGE_IOC_4 1412 { 1413 fCONFIG_PAGE_HEADER Header; /* 00h */ 1414 U8 ActiveSEP; /* 04h */ 1415 U8 MaxSEP; /* 05h */ 1416 U16 Reserved1; /* 06h */ 1417 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 1418 } fCONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 1419 IOCPage4_t, MPI_POINTER pIOCPage4_t; 1420 1421 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 1422 1423 1424 /**************************************************************************** 1425 * SCSI Port Config Pages 1426 ****************************************************************************/ 1427 1428 typedef struct _CONFIG_PAGE_SCSI_PORT_0 1429 { 1430 fCONFIG_PAGE_HEADER Header; /* 00h */ 1431 U32 Capabilities; /* 04h */ 1432 U32 PhysicalInterface; /* 08h */ 1433 } fCONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 1434 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 1435 1436 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01) 1437 1438 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 1439 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 1440 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 1441 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1442 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1443 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 1444 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 1445 1446 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 1447 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 1448 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 1449 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 1450 1451 1452 typedef struct _CONFIG_PAGE_SCSI_PORT_1 1453 { 1454 fCONFIG_PAGE_HEADER Header; /* 00h */ 1455 U32 Configuration; /* 04h */ 1456 U32 OnBusTimerValue; /* 08h */ 1457 } fCONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 1458 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 1459 1460 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02) 1461 1462 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 1463 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 1464 1465 1466 typedef struct _MPI_DEVICE_INFO 1467 { 1468 U8 Timeout; /* 00h */ 1469 U8 SyncFactor; /* 01h */ 1470 U16 DeviceFlags; /* 02h */ 1471 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 1472 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 1473 1474 typedef struct _CONFIG_PAGE_SCSI_PORT_2 1475 { 1476 fCONFIG_PAGE_HEADER Header; /* 00h */ 1477 U32 PortFlags; /* 04h */ 1478 U32 PortSettings; /* 08h */ 1479 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 1480 } fCONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 1481 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 1482 1483 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01) 1484 1485 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 1486 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 1487 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1488 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 1489 1490 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 1491 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 1492 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 1493 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 1494 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 1495 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 1496 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 1497 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 1498 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 1499 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 1500 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 1501 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 1502 1503 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 1504 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 1505 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 1506 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 1507 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 1508 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 1509 1510 1511 /**************************************************************************** 1512 * SCSI Target Device Config Pages 1513 ****************************************************************************/ 1514 1515 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 1516 { 1517 fCONFIG_PAGE_HEADER Header; /* 00h */ 1518 U32 NegotiatedParameters; /* 04h */ 1519 U32 Information; /* 08h */ 1520 } fCONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 1521 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 1522 1523 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x02) 1524 1525 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 1526 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 1527 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 1528 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 1529 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 1530 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 1531 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 1532 1533 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 1534 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 1535 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 1536 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 1537 1538 1539 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 1540 { 1541 fCONFIG_PAGE_HEADER Header; /* 00h */ 1542 U32 RequestedParameters; /* 04h */ 1543 U32 Reserved; /* 08h */ 1544 U32 Configuration; /* 0Ch */ 1545 } fCONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 1546 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 1547 1548 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x03) 1549 1550 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 1551 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 1552 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 1553 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1554 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1555 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 1556 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 1557 1558 #define MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK (0x00000003) 1559 #define MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK (0x00000300) 1560 1561 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 1562 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 1563 1564 1565 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 1566 { 1567 fCONFIG_PAGE_HEADER Header; /* 00h */ 1568 U32 DomainValidation; /* 04h */ 1569 U32 ParityPipeSelect; /* 08h */ 1570 U32 DataPipeSelect; /* 0Ch */ 1571 } fCONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 1572 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 1573 1574 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x00) 1575 1576 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 1577 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 1578 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 1579 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 1580 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 1581 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 1582 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 1583 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 1584 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 1585 1586 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 1587 1588 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 1589 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 1590 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 1591 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 1592 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 1593 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 1594 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 1595 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 1596 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 1597 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 1598 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 1599 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 1600 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 1601 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 1602 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 1603 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 1604 1605 1606 /**************************************************************************** 1607 * FC Port Config Pages 1608 ****************************************************************************/ 1609 1610 typedef struct _CONFIG_PAGE_FC_PORT_0 1611 { 1612 fCONFIG_PAGE_HEADER Header; /* 00h */ 1613 U32 Flags; /* 04h */ 1614 U8 MPIPortNumber; /* 08h */ 1615 U8 LinkType; /* 09h */ 1616 U8 PortState; /* 0Ah */ 1617 U8 Reserved; /* 0Bh */ 1618 U32 PortIdentifier; /* 0Ch */ 1619 U64 WWNN; /* 10h */ 1620 U64 WWPN; /* 18h */ 1621 U32 SupportedServiceClass; /* 20h */ 1622 U32 SupportedSpeeds; /* 24h */ 1623 U32 CurrentSpeed; /* 28h */ 1624 U32 MaxFrameSize; /* 2Ch */ 1625 U64 FabricWWNN; /* 30h */ 1626 U64 FabricWWPN; /* 38h */ 1627 U32 DiscoveredPortsCount; /* 40h */ 1628 U32 MaxInitiators; /* 44h */ 1629 } fCONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 1630 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 1631 1632 #define MPI_FCPORTPAGE0_PAGEVERSION (0x01) 1633 1634 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 1635 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 1636 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 1637 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 1638 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 1639 1640 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 1641 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 1642 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000030) 1643 1644 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 1645 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 1646 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 1647 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 1648 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 1649 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 1650 1651 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 1652 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 1653 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 1654 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 1655 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 1656 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 1657 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 1658 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 1659 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 1660 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 1661 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 1662 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 1663 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 1664 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 1665 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 1666 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 1667 1668 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 1669 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 1670 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 1671 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 1672 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 1673 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 1674 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 1675 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 1676 1677 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 1678 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 1679 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 1680 1681 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 1682 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1683 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1684 1685 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1686 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1687 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1688 1689 1690 typedef struct _CONFIG_PAGE_FC_PORT_1 1691 { 1692 fCONFIG_PAGE_HEADER Header; /* 00h */ 1693 U32 Flags; /* 04h */ 1694 U64 NoSEEPROMWWNN; /* 08h */ 1695 U64 NoSEEPROMWWPN; /* 10h */ 1696 U8 HardALPA; /* 18h */ 1697 U8 LinkConfig; /* 19h */ 1698 U8 TopologyConfig; /* 1Ah */ 1699 U8 Reserved; /* 1Bh */ 1700 } fCONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1701 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1702 1703 #define MPI_FCPORTPAGE1_PAGEVERSION (0x02) 1704 1705 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1706 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1707 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1708 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1709 1710 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1711 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1712 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1713 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1714 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1715 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1716 1717 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1718 1719 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1720 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1721 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1722 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1723 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1724 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1725 1726 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1727 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1728 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1729 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1730 1731 1732 typedef struct _CONFIG_PAGE_FC_PORT_2 1733 { 1734 fCONFIG_PAGE_HEADER Header; /* 00h */ 1735 U8 NumberActive; /* 04h */ 1736 U8 ALPA[127]; /* 05h */ 1737 } fCONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1738 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1739 1740 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1741 1742 1743 typedef struct _WWN_FORMAT 1744 { 1745 U64 WWNN; /* 00h */ 1746 U64 WWPN; /* 08h */ 1747 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1748 WWNFormat, MPI_POINTER pWWNFormat; 1749 1750 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1751 { 1752 WWN_FORMAT WWN; 1753 U32 Did; 1754 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1755 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1756 1757 typedef struct _FC_PORT_PERSISTENT 1758 { 1759 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1760 U8 TargetID; /* 10h */ 1761 U8 Bus; /* 11h */ 1762 U16 Flags; /* 12h */ 1763 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1764 PersistentData_t, MPI_POINTER pPersistentData_t; 1765 1766 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1767 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1768 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1769 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1770 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1771 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1772 1773 /* 1774 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1775 * one and check Header.PageLength at runtime. 1776 */ 1777 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1778 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1779 #endif 1780 1781 typedef struct _CONFIG_PAGE_FC_PORT_3 1782 { 1783 fCONFIG_PAGE_HEADER Header; /* 00h */ 1784 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1785 } fCONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1786 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1787 1788 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1789 1790 1791 typedef struct _CONFIG_PAGE_FC_PORT_4 1792 { 1793 fCONFIG_PAGE_HEADER Header; /* 00h */ 1794 U32 PortFlags; /* 04h */ 1795 U32 PortSettings; /* 08h */ 1796 } fCONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1797 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1798 1799 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1800 1801 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1802 1803 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1804 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1805 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1806 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1807 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 1808 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 1809 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 1810 1811 1812 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 1813 { 1814 U8 Flags; /* 00h */ 1815 U8 AliasAlpa; /* 01h */ 1816 U16 Reserved; /* 02h */ 1817 U64 AliasWWNN; /* 04h */ 1818 U64 AliasWWPN; /* 0Ch */ 1819 } fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1820 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1821 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1822 1823 /* 1824 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1825 * one and check Header.PageLength at runtime. 1826 */ 1827 #ifndef MPI_FC_PORT_PAGE_5_ALIAS_MAX 1828 #define MPI_FC_PORT_PAGE_5_ALIAS_MAX (1) 1829 #endif 1830 1831 typedef struct _CONFIG_PAGE_FC_PORT_5 1832 { 1833 fCONFIG_PAGE_HEADER Header; /* 00h */ 1834 fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX];/* 04h */ 1835 } fCONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1836 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1837 1838 #define MPI_FCPORTPAGE5_PAGEVERSION (0x00) 1839 1840 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID (0x01) 1841 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID (0x02) 1842 1843 1844 typedef struct _CONFIG_PAGE_FC_PORT_6 1845 { 1846 fCONFIG_PAGE_HEADER Header; /* 00h */ 1847 U32 Reserved; /* 04h */ 1848 U64 TimeSinceReset; /* 08h */ 1849 U64 TxFrames; /* 10h */ 1850 U64 RxFrames; /* 18h */ 1851 U64 TxWords; /* 20h */ 1852 U64 RxWords; /* 28h */ 1853 U64 LipCount; /* 30h */ 1854 U64 NosCount; /* 38h */ 1855 U64 ErrorFrames; /* 40h */ 1856 U64 DumpedFrames; /* 48h */ 1857 U64 LinkFailureCount; /* 50h */ 1858 U64 LossOfSyncCount; /* 58h */ 1859 U64 LossOfSignalCount; /* 60h */ 1860 U64 PrimativeSeqErrCount; /* 68h */ 1861 U64 InvalidTxWordCount; /* 70h */ 1862 U64 InvalidCrcCount; /* 78h */ 1863 U64 FcpInitiatorIoCount; /* 80h */ 1864 } fCONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 1865 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 1866 1867 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 1868 1869 1870 typedef struct _CONFIG_PAGE_FC_PORT_7 1871 { 1872 fCONFIG_PAGE_HEADER Header; /* 00h */ 1873 U32 Reserved; /* 04h */ 1874 U8 PortSymbolicName[256]; /* 08h */ 1875 } fCONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 1876 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 1877 1878 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 1879 1880 1881 typedef struct _CONFIG_PAGE_FC_PORT_8 1882 { 1883 fCONFIG_PAGE_HEADER Header; /* 00h */ 1884 U32 BitVector[8]; /* 04h */ 1885 } fCONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 1886 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 1887 1888 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 1889 1890 1891 typedef struct _CONFIG_PAGE_FC_PORT_9 1892 { 1893 fCONFIG_PAGE_HEADER Header; /* 00h */ 1894 U32 Reserved; /* 04h */ 1895 U64 GlobalWWPN; /* 08h */ 1896 U64 GlobalWWNN; /* 10h */ 1897 U32 UnitType; /* 18h */ 1898 U32 PhysicalPortNumber; /* 1Ch */ 1899 U32 NumAttachedNodes; /* 20h */ 1900 U16 IPVersion; /* 24h */ 1901 U16 UDPPortNumber; /* 26h */ 1902 U8 IPAddress[16]; /* 28h */ 1903 U16 Reserved1; /* 38h */ 1904 U16 TopologyDiscoveryFlags; /* 3Ah */ 1905 } fCONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 1906 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 1907 1908 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 1909 1910 1911 /**************************************************************************** 1912 * FC Device Config Pages 1913 ****************************************************************************/ 1914 1915 typedef struct _CONFIG_PAGE_FC_DEVICE_0 1916 { 1917 fCONFIG_PAGE_HEADER Header; /* 00h */ 1918 U64 WWNN; /* 04h */ 1919 U64 WWPN; /* 0Ch */ 1920 U32 PortIdentifier; /* 14h */ 1921 U8 Protocol; /* 18h */ 1922 U8 Flags; /* 19h */ 1923 U16 BBCredit; /* 1Ah */ 1924 U16 MaxRxFrameSize; /* 1Ch */ 1925 U8 Reserved1; /* 1Eh */ 1926 U8 PortNumber; /* 1Fh */ 1927 U8 FcPhLowestVersion; /* 20h */ 1928 U8 FcPhHighestVersion; /* 21h */ 1929 U8 CurrentTargetID; /* 22h */ 1930 U8 CurrentBus; /* 23h */ 1931 } fCONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 1932 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 1933 1934 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02) 1935 1936 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 1937 1938 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 1939 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 1940 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 1941 1942 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 1943 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 1944 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 1945 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 1946 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 1947 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 1948 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 1949 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 1950 1951 1952 /**************************************************************************** 1953 * RAID Volume Config Pages 1954 ****************************************************************************/ 1955 1956 typedef struct _RAID_VOL0_PHYS_DISK 1957 { 1958 U16 Reserved; /* 00h */ 1959 U8 PhysDiskMap; /* 02h */ 1960 U8 PhysDiskNum; /* 03h */ 1961 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 1962 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 1963 1964 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1965 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1966 1967 typedef struct _RAID_VOL0_STATUS 1968 { 1969 U8 Flags; /* 00h */ 1970 U8 State; /* 01h */ 1971 U16 Reserved; /* 02h */ 1972 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 1973 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 1974 1975 /* RAID Volume Page 0 VolumeStatus defines */ 1976 1977 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 1978 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 1979 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 1980 1981 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 1982 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 1983 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 1984 1985 typedef struct _RAID_VOL0_SETTINGS 1986 { 1987 U16 Settings; /* 00h */ 1988 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1989 U8 Reserved; /* 02h */ 1990 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 1991 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 1992 1993 /* RAID Volume Page 0 VolumeSettings defines */ 1994 1995 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 1996 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 1997 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 1998 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 1999 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 2000 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 2001 2002 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 2003 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 2004 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 2005 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 2006 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 2007 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 2008 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 2009 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 2010 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 2011 2012 /* 2013 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2014 * one and check Header.PageLength at runtime. 2015 */ 2016 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 2017 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 2018 #endif 2019 2020 typedef struct _CONFIG_PAGE_RAID_VOL_0 2021 { 2022 fCONFIG_PAGE_HEADER Header; /* 00h */ 2023 U8 VolumeID; /* 04h */ 2024 U8 VolumeBus; /* 05h */ 2025 U8 VolumeIOC; /* 06h */ 2026 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 2027 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 2028 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 2029 U32 MaxLBA; /* 10h */ 2030 U32 Reserved1; /* 14h */ 2031 U32 StripeSize; /* 18h */ 2032 U32 Reserved2; /* 1Ch */ 2033 U32 Reserved3; /* 20h */ 2034 U8 NumPhysDisks; /* 24h */ 2035 U8 Reserved4; /* 25h */ 2036 U16 Reserved5; /* 26h */ 2037 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 2038 } fCONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 2039 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 2040 2041 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x00) 2042 2043 2044 /**************************************************************************** 2045 * RAID Physical Disk Config Pages 2046 ****************************************************************************/ 2047 2048 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 2049 { 2050 U8 ErrorCdbByte; /* 00h */ 2051 U8 ErrorSenseKey; /* 01h */ 2052 U16 Reserved; /* 02h */ 2053 U16 ErrorCount; /* 04h */ 2054 U8 ErrorASC; /* 06h */ 2055 U8 ErrorASCQ; /* 07h */ 2056 U16 SmartCount; /* 08h */ 2057 U8 SmartASC; /* 0Ah */ 2058 U8 SmartASCQ; /* 0Bh */ 2059 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 2060 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 2061 2062 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 2063 { 2064 U8 VendorID[8]; /* 00h */ 2065 U8 ProductID[16]; /* 08h */ 2066 U8 ProductRevLevel[4]; /* 18h */ 2067 U8 Info[32]; /* 1Ch */ 2068 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 2069 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 2070 2071 typedef struct _RAID_PHYS_DISK0_SETTINGS 2072 { 2073 U8 SepID; /* 00h */ 2074 U8 SepBus; /* 01h */ 2075 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2076 U8 PhysDiskSettings; /* 03h */ 2077 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 2078 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 2079 2080 typedef struct _RAID_PHYS_DISK0_STATUS 2081 { 2082 U8 Flags; /* 00h */ 2083 U8 State; /* 01h */ 2084 U16 Reserved; /* 02h */ 2085 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 2086 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 2087 2088 /* RAID Volume 2 IM Physical Disk DiskStatus flags */ 2089 2090 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 2091 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 2092 2093 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 2094 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 2095 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 2096 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 2097 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 2098 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 2099 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 2100 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 2101 2102 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 2103 { 2104 fCONFIG_PAGE_HEADER Header; /* 00h */ 2105 U8 PhysDiskID; /* 04h */ 2106 U8 PhysDiskBus; /* 05h */ 2107 U8 PhysDiskIOC; /* 06h */ 2108 U8 PhysDiskNum; /* 07h */ 2109 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 2110 U32 Reserved1; /* 0Ch */ 2111 U32 Reserved2; /* 10h */ 2112 U32 Reserved3; /* 14h */ 2113 U8 DiskIdentifier[16]; /* 18h */ 2114 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 2115 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 2116 U32 MaxLBA; /* 68h */ 2117 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 2118 } fCONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 2119 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 2120 2121 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00) 2122 2123 2124 /**************************************************************************** 2125 * LAN Config Pages 2126 ****************************************************************************/ 2127 2128 typedef struct _CONFIG_PAGE_LAN_0 2129 { 2130 ConfigPageHeader_t Header; /* 00h */ 2131 U16 TxRxModes; /* 04h */ 2132 U16 Reserved; /* 06h */ 2133 U32 PacketPrePad; /* 08h */ 2134 } fCONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 2135 LANPage0_t, MPI_POINTER pLANPage0_t; 2136 2137 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 2138 2139 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 2140 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 2141 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 2142 2143 typedef struct _CONFIG_PAGE_LAN_1 2144 { 2145 ConfigPageHeader_t Header; /* 00h */ 2146 U16 Reserved; /* 04h */ 2147 U8 CurrentDeviceState; /* 06h */ 2148 U8 Reserved1; /* 07h */ 2149 U32 MinPacketSize; /* 08h */ 2150 U32 MaxPacketSize; /* 0Ch */ 2151 U32 HardwareAddressLow; /* 10h */ 2152 U32 HardwareAddressHigh; /* 14h */ 2153 U32 MaxWireSpeedLow; /* 18h */ 2154 U32 MaxWireSpeedHigh; /* 1Ch */ 2155 U32 BucketsRemaining; /* 20h */ 2156 U32 MaxReplySize; /* 24h */ 2157 U32 NegWireSpeedLow; /* 28h */ 2158 U32 NegWireSpeedHigh; /* 2Ch */ 2159 } fCONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 2160 LANPage1_t, MPI_POINTER pLANPage1_t; 2161 2162 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 2163 2164 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 2165 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 2166 2167 #endif 2168 2169 2170 /* 2171 * Copyright (c) 2000, 2001 by LSI Logic Corporation 2172 * 2173 * Redistribution and use in source and binary forms, with or without 2174 * modification, are permitted provided that the following conditions 2175 * are met: 2176 * 1. Redistributions of source code must retain the above copyright 2177 * notice immediately at the beginning of the file, without modification, 2178 * this list of conditions, and the following disclaimer. 2179 * 2. The name of the author may not be used to endorse or promote products 2180 * derived from this software without specific prior written permission. 2181 * 2182 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2183 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2184 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2185 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2186 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2187 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2188 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2189 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2190 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2191 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2192 * SUCH DAMAGE. 2193 * 2194 * 2195 * Name: MPI_FC.H 2196 * Title: MPI Fibre Channel messages and structures 2197 * Creation Date: June 12, 2000 2198 * 2199 * MPI Version: 01.02.02 2200 * 2201 * Version History 2202 * --------------- 2203 * 2204 * Date Version Description 2205 * -------- -------- ------------------------------------------------------ 2206 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 2207 * 06-06-00 01.00.01 Update version number for 1.0 release. 2208 * 06-12-00 01.00.02 Added _MSG_FC_ABORT_REPLY structure. 2209 * 11-02-00 01.01.01 Original release for post 1.0 work 2210 * 12-04-00 01.01.02 Added messages for Common Transport Send and 2211 * Primitive Send. 2212 * 01-09-01 01.01.03 Modifed some of the new flags to have an MPI prefix 2213 * and modified the FcPrimitiveSend flags. 2214 * 01-25-01 01.01.04 Move InitiatorIndex in LinkServiceRsp reply to a larger 2215 * field. 2216 * Added FC_ABORT_TYPE_CT_SEND_REQUEST and 2217 * FC_ABORT_TYPE_EXLINKSEND_REQUEST for FcAbort request. 2218 * Added MPI_FC_PRIM_SEND_FLAGS_STOP_SEND. 2219 * 02-20-01 01.01.05 Started using MPI_POINTER. 2220 * 03-27-01 01.01.06 Added Flags field to MSG_LINK_SERVICE_BUFFER_POST_REPLY 2221 * and defined MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED. 2222 * Added MPI_FC_PRIM_SEND_FLAGS_RESET_LINK define. 2223 * Added structure offset comments. 2224 * 04-09-01 01.01.07 Added RspLength field to MSG_LINK_SERVICE_RSP_REQUEST. 2225 * 08-08-01 01.02.01 Original release for v1.2 work. 2226 * 09-28-01 01.02.02 Change name of reserved field in 2227 * MSG_LINK_SERVICE_RSP_REPLY. 2228 * -------------------------------------------------------------------------- 2229 */ 2230 2231 #ifndef MPI_FC_H 2232 #define MPI_FC_H 2233 2234 2235 /***************************************************************************** 2236 * 2237 * F C T a r g e t M o d e M e s s a g e s 2238 * 2239 *****************************************************************************/ 2240 2241 /****************************************************************************/ 2242 /* Link Service Buffer Post messages */ 2243 /****************************************************************************/ 2244 2245 typedef struct _MSG_LINK_SERVICE_BUFFER_POST_REQUEST 2246 { 2247 U8 BufferPostFlags; /* 00h */ 2248 U8 BufferCount; /* 01h */ 2249 U8 ChainOffset; /* 02h */ 2250 U8 Function; /* 03h */ 2251 U16 Reserved; /* 04h */ 2252 U8 Reserved1; /* 06h */ 2253 U8 MsgFlags; /* 07h */ 2254 U32 MsgContext; /* 08h */ 2255 SGE_TRANS_SIMPLE_UNION SGL; 2256 } MSG_LINK_SERVICE_BUFFER_POST_REQUEST, 2257 MPI_POINTER PTR_MSG_LINK_SERVICE_BUFFER_POST_REQUEST, 2258 LinkServiceBufferPostRequest_t, MPI_POINTER pLinkServiceBufferPostRequest_t; 2259 2260 #define LINK_SERVICE_BUFFER_POST_FLAGS_PORT_MASK (0x01) 2261 2262 typedef struct _WWNFORMAT 2263 { 2264 U32 PortNameHigh; /* 00h */ 2265 U32 PortNameLow; /* 04h */ 2266 U32 NodeNameHigh; /* 08h */ 2267 U32 NodeNameLow; /* 0Ch */ 2268 } WWNFORMAT, 2269 WwnFormat_t; 2270 2271 /* Link Service Buffer Post Reply */ 2272 typedef struct _MSG_LINK_SERVICE_BUFFER_POST_REPLY 2273 { 2274 U8 Flags; /* 00h */ 2275 U8 Reserved; /* 01h */ 2276 U8 MsgLength; /* 02h */ 2277 U8 Function; /* 03h */ 2278 U16 Reserved1; /* 04h */ 2279 U8 PortNumber; /* 06h */ 2280 U8 MsgFlags; /* 07h */ 2281 U32 MsgContext; /* 08h */ 2282 U16 Reserved2; /* 0Ch */ 2283 U16 IOCStatus; /* 0Eh */ 2284 U32 IOCLogInfo; /* 10h */ 2285 U32 TransferLength; /* 14h */ 2286 U32 TransactionContext; /* 18h */ 2287 U32 Rctl_Did; /* 1Ch */ 2288 U32 Csctl_Sid; /* 20h */ 2289 U32 Type_Fctl; /* 24h */ 2290 U16 SeqCnt; /* 28h */ 2291 U8 Dfctl; /* 2Ah */ 2292 U8 SeqId; /* 2Bh */ 2293 U16 Rxid; /* 2Ch */ 2294 U16 Oxid; /* 2Eh */ 2295 U32 Parameter; /* 30h */ 2296 WWNFORMAT Wwn; /* 34h */ 2297 } MSG_LINK_SERVICE_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_LINK_SERVICE_BUFFER_POST_REPLY, 2298 LinkServiceBufferPostReply_t, MPI_POINTER pLinkServiceBufferPostReply_t; 2299 2300 #define MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED (0x80) 2301 2302 #define MPI_FC_DID_MASK (0x00FFFFFF) 2303 #define MPI_FC_DID_SHIFT (0) 2304 #define MPI_FC_RCTL_MASK (0xFF000000) 2305 #define MPI_FC_RCTL_SHIFT (24) 2306 #define MPI_FC_SID_MASK (0x00FFFFFF) 2307 #define MPI_FC_SID_SHIFT (0) 2308 #define MPI_FC_CSCTL_MASK (0xFF000000) 2309 #define MPI_FC_CSCTL_SHIFT (24) 2310 #define MPI_FC_FCTL_MASK (0x00FFFFFF) 2311 #define MPI_FC_FCTL_SHIFT (0) 2312 #define MPI_FC_TYPE_MASK (0xFF000000) 2313 #define MPI_FC_TYPE_SHIFT (24) 2314 2315 /* obsolete name for the above */ 2316 #define FCP_TARGET_DID_MASK (0x00FFFFFF) 2317 #define FCP_TARGET_DID_SHIFT (0) 2318 #define FCP_TARGET_RCTL_MASK (0xFF000000) 2319 #define FCP_TARGET_RCTL_SHIFT (24) 2320 #define FCP_TARGET_SID_MASK (0x00FFFFFF) 2321 #define FCP_TARGET_SID_SHIFT (0) 2322 #define FCP_TARGET_CSCTL_MASK (0xFF000000) 2323 #define FCP_TARGET_CSCTL_SHIFT (24) 2324 #define FCP_TARGET_FCTL_MASK (0x00FFFFFF) 2325 #define FCP_TARGET_FCTL_SHIFT (0) 2326 #define FCP_TARGET_TYPE_MASK (0xFF000000) 2327 #define FCP_TARGET_TYPE_SHIFT (24) 2328 2329 2330 /****************************************************************************/ 2331 /* Link Service Response messages */ 2332 /****************************************************************************/ 2333 2334 typedef struct _MSG_LINK_SERVICE_RSP_REQUEST 2335 { 2336 U8 RspFlags; /* 00h */ 2337 U8 RspLength; /* 01h */ 2338 U8 ChainOffset; /* 02h */ 2339 U8 Function; /* 03h */ 2340 U16 Reserved1; /* 04h */ 2341 U8 Reserved2; /* 06h */ 2342 U8 MsgFlags; /* 07h */ 2343 U32 MsgContext; /* 08h */ 2344 U32 Rctl_Did; /* 0Ch */ 2345 U32 Csctl_Sid; /* 10h */ 2346 U32 Type_Fctl; /* 14h */ 2347 U16 SeqCnt; /* 18h */ 2348 U8 Dfctl; /* 1Ah */ 2349 U8 SeqId; /* 1Bh */ 2350 U16 Rxid; /* 1Ch */ 2351 U16 Oxid; /* 1Eh */ 2352 U32 Parameter; /* 20h */ 2353 SGE_SIMPLE_UNION SGL; /* 24h */ 2354 } MSG_LINK_SERVICE_RSP_REQUEST, MPI_POINTER PTR_MSG_LINK_SERVICE_RSP_REQUEST, 2355 LinkServiceRspRequest_t, MPI_POINTER pLinkServiceRspRequest_t; 2356 2357 #define LINK_SERVICE_RSP_FLAGS_IMMEDIATE (0x80) 2358 #define LINK_SERVICE_RSP_FLAGS_PORT_MASK (0x01) 2359 2360 2361 /* Link Service Response Reply */ 2362 typedef struct _MSG_LINK_SERVICE_RSP_REPLY 2363 { 2364 U16 Reserved; /* 00h */ 2365 U8 MsgLength; /* 02h */ 2366 U8 Function; /* 03h */ 2367 U16 Reserved1; /* 04h */ 2368 U8 Reserved_0100_InitiatorIndex; /* 06h */ /* obsolete InitiatorIndex */ 2369 U8 MsgFlags; /* 07h */ 2370 U32 MsgContext; /* 08h */ 2371 U16 Reserved3; /* 0Ch */ 2372 U16 IOCStatus; /* 0Eh */ 2373 U32 IOCLogInfo; /* 10h */ 2374 U32 InitiatorIndex; /* 14h */ 2375 } MSG_LINK_SERVICE_RSP_REPLY, MPI_POINTER PTR_MSG_LINK_SERVICE_RSP_REPLY, 2376 LinkServiceRspReply_t, MPI_POINTER pLinkServiceRspReply_t; 2377 2378 2379 /****************************************************************************/ 2380 /* Extended Link Service Send messages */ 2381 /****************************************************************************/ 2382 2383 typedef struct _MSG_EXLINK_SERVICE_SEND_REQUEST 2384 { 2385 U8 SendFlags; /* 00h */ 2386 U8 Reserved; /* 01h */ 2387 U8 ChainOffset; /* 02h */ 2388 U8 Function; /* 03h */ 2389 U32 MsgFlags_Did; /* 04h */ 2390 U32 MsgContext; /* 08h */ 2391 U32 ElsCommandCode; /* 0Ch */ 2392 SGE_SIMPLE_UNION SGL; /* 10h */ 2393 } MSG_EXLINK_SERVICE_SEND_REQUEST, MPI_POINTER PTR_MSG_EXLINK_SERVICE_SEND_REQUEST, 2394 ExLinkServiceSendRequest_t, MPI_POINTER pExLinkServiceSendRequest_t; 2395 2396 #define EX_LINK_SERVICE_SEND_DID_MASK (0x00FFFFFF) 2397 #define EX_LINK_SERVICE_SEND_DID_SHIFT (0) 2398 #define EX_LINK_SERVICE_SEND_MSGFLAGS_MASK (0xFF000000) 2399 #define EX_LINK_SERVICE_SEND_MSGFLAGS_SHIFT (24) 2400 2401 2402 /* Extended Link Service Send Reply */ 2403 typedef struct _MSG_EXLINK_SERVICE_SEND_REPLY 2404 { 2405 U16 Reserved; /* 00h */ 2406 U8 MsgLength; /* 02h */ 2407 U8 Function; /* 03h */ 2408 U16 Reserved1; /* 04h */ 2409 U8 Reserved2; /* 06h */ 2410 U8 MsgFlags; /* 07h */ 2411 U32 MsgContext; /* 08h */ 2412 U16 Reserved3; /* 0Ch */ 2413 U16 IOCStatus; /* 0Eh */ 2414 U32 IOCLogInfo; /* 10h */ 2415 U32 ResponseLength; /* 14h */ 2416 } MSG_EXLINK_SERVICE_SEND_REPLY, MPI_POINTER PTR_MSG_EXLINK_SERVICE_SEND_REPLY, 2417 ExLinkServiceSendReply_t, MPI_POINTER pExLinkServiceSendReply_t; 2418 2419 /****************************************************************************/ 2420 /* FC Abort messages */ 2421 /****************************************************************************/ 2422 2423 typedef struct _MSG_FC_ABORT_REQUEST 2424 { 2425 U8 AbortFlags; /* 00h */ 2426 U8 AbortType; /* 01h */ 2427 U8 ChainOffset; /* 02h */ 2428 U8 Function; /* 03h */ 2429 U16 Reserved1; /* 04h */ 2430 U8 Reserved2; /* 06h */ 2431 U8 MsgFlags; /* 07h */ 2432 U32 MsgContext; /* 08h */ 2433 U32 TransactionContextToAbort; /* 0Ch */ 2434 } MSG_FC_ABORT_REQUEST, MPI_POINTER PTR_MSG_FC_ABORT_REQUEST, 2435 FcAbortRequest_t, MPI_POINTER pFcAbortRequest_t; 2436 2437 #define FC_ABORT_FLAG_PORT_MASK (0x01) 2438 2439 #define FC_ABORT_TYPE_ALL_FC_BUFFERS (0x00) 2440 #define FC_ABORT_TYPE_EXACT_FC_BUFFER (0x01) 2441 #define FC_ABORT_TYPE_CT_SEND_REQUEST (0x02) 2442 #define FC_ABORT_TYPE_EXLINKSEND_REQUEST (0x03) 2443 2444 /* FC Abort Reply */ 2445 typedef struct _MSG_FC_ABORT_REPLY 2446 { 2447 U16 Reserved; /* 00h */ 2448 U8 MsgLength; /* 02h */ 2449 U8 Function; /* 03h */ 2450 U16 Reserved1; /* 04h */ 2451 U8 Reserved2; /* 06h */ 2452 U8 MsgFlags; /* 07h */ 2453 U32 MsgContext; /* 08h */ 2454 U16 Reserved3; /* 0Ch */ 2455 U16 IOCStatus; /* 0Eh */ 2456 U32 IOCLogInfo; /* 10h */ 2457 } MSG_FC_ABORT_REPLY, MPI_POINTER PTR_MSG_FC_ABORT_REPLY, 2458 FcAbortReply_t, MPI_POINTER pFcAbortReply_t; 2459 2460 2461 /****************************************************************************/ 2462 /* FC Common Transport Send messages */ 2463 /****************************************************************************/ 2464 2465 typedef struct _MSG_FC_COMMON_TRANSPORT_SEND_REQUEST 2466 { 2467 U8 SendFlags; /* 00h */ 2468 U8 Reserved; /* 01h */ 2469 U8 ChainOffset; /* 02h */ 2470 U8 Function; /* 03h */ 2471 U32 MsgFlags_Did; /* 04h */ 2472 U32 MsgContext; /* 08h */ 2473 U16 CTCommandCode; /* 0Ch */ 2474 U8 FsType; /* 0Eh */ 2475 U8 Reserved1; /* 0Fh */ 2476 SGE_SIMPLE_UNION SGL; /* 10h */ 2477 } MSG_FC_COMMON_TRANSPORT_SEND_REQUEST, 2478 MPI_POINTER PTR_MSG_FC_COMMON_TRANSPORT_SEND_REQUEST, 2479 FcCommonTransportSendRequest_t, MPI_POINTER pFcCommonTransportSendRequest_t; 2480 2481 #define MPI_FC_CT_SEND_DID_MASK (0x00FFFFFF) 2482 #define MPI_FC_CT_SEND_DID_SHIFT (0) 2483 #define MPI_FC_CT_SEND_MSGFLAGS_MASK (0xFF000000) 2484 #define MPI_FC_CT_SEND_MSGFLAGS_SHIFT (24) 2485 2486 2487 /* FC Common Transport Send Reply */ 2488 typedef struct _MSG_FC_COMMON_TRANSPORT_SEND_REPLY 2489 { 2490 U16 Reserved; /* 00h */ 2491 U8 MsgLength; /* 02h */ 2492 U8 Function; /* 03h */ 2493 U16 Reserved1; /* 04h */ 2494 U8 Reserved2; /* 06h */ 2495 U8 MsgFlags; /* 07h */ 2496 U32 MsgContext; /* 08h */ 2497 U16 Reserved3; /* 0Ch */ 2498 U16 IOCStatus; /* 0Eh */ 2499 U32 IOCLogInfo; /* 10h */ 2500 U32 ResponseLength; /* 14h */ 2501 } MSG_FC_COMMON_TRANSPORT_SEND_REPLY, MPI_POINTER PTR_MSG_FC_COMMON_TRANSPORT_SEND_REPLY, 2502 FcCommonTransportSendReply_t, MPI_POINTER pFcCommonTransportSendReply_t; 2503 2504 2505 /****************************************************************************/ 2506 /* FC Primitive Send messages */ 2507 /****************************************************************************/ 2508 2509 typedef struct _MSG_FC_PRIMITIVE_SEND_REQUEST 2510 { 2511 U8 SendFlags; /* 00h */ 2512 U8 Reserved; /* 01h */ 2513 U8 ChainOffset; /* 02h */ 2514 U8 Function; /* 03h */ 2515 U16 Reserved1; /* 04h */ 2516 U8 Reserved2; /* 06h */ 2517 U8 MsgFlags; /* 07h */ 2518 U32 MsgContext; /* 08h */ 2519 U8 FcPrimitive[4]; /* 0Ch */ 2520 } MSG_FC_PRIMITIVE_SEND_REQUEST, MPI_POINTER PTR_MSG_FC_PRIMITIVE_SEND_REQUEST, 2521 FcPrimitiveSendRequest_t, MPI_POINTER pFcPrimitiveSendRequest_t; 2522 2523 #define MPI_FC_PRIM_SEND_FLAGS_PORT_MASK (0x01) 2524 #define MPI_FC_PRIM_SEND_FLAGS_RESET_LINK (0x04) 2525 #define MPI_FC_PRIM_SEND_FLAGS_STOP_SEND (0x08) 2526 #define MPI_FC_PRIM_SEND_FLAGS_SEND_ONCE (0x10) 2527 #define MPI_FC_PRIM_SEND_FLAGS_SEND_AROUND (0x20) 2528 #define MPI_FC_PRIM_SEND_FLAGS_UNTIL_FULL (0x40) 2529 #define MPI_FC_PRIM_SEND_FLAGS_FOREVER (0x80) 2530 2531 /* FC Primitive Send Reply */ 2532 typedef struct _MSG_FC_PRIMITIVE_SEND_REPLY 2533 { 2534 U8 SendFlags; /* 00h */ 2535 U8 Reserved; /* 01h */ 2536 U8 MsgLength; /* 02h */ 2537 U8 Function; /* 03h */ 2538 U16 Reserved1; /* 04h */ 2539 U8 Reserved2; /* 06h */ 2540 U8 MsgFlags; /* 07h */ 2541 U32 MsgContext; /* 08h */ 2542 U16 Reserved3; /* 0Ch */ 2543 U16 IOCStatus; /* 0Eh */ 2544 U32 IOCLogInfo; /* 10h */ 2545 } MSG_FC_PRIMITIVE_SEND_REPLY, MPI_POINTER PTR_MSG_FC_PRIMITIVE_SEND_REPLY, 2546 FcPrimitiveSendReply_t, MPI_POINTER pFcPrimitiveSendReply_t; 2547 2548 #endif 2549 2550 2551 /* 2552 * Copyright (c) 2000, 2001 by LSI Logic Corporation 2553 * 2554 * Redistribution and use in source and binary forms, with or without 2555 * modification, are permitted provided that the following conditions 2556 * are met: 2557 * 1. Redistributions of source code must retain the above copyright 2558 * notice immediately at the beginning of the file, without modification, 2559 * this list of conditions, and the following disclaimer. 2560 * 2. The name of the author may not be used to endorse or promote products 2561 * derived from this software without specific prior written permission. 2562 * 2563 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2564 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2565 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2566 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2567 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2568 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2569 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2570 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2571 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2572 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2573 * SUCH DAMAGE. 2574 * 2575 * 2576 * Name: MPI_INIT.H 2577 * Title: MPI initiator mode messages and structures 2578 * Creation Date: June 8, 2000 2579 * 2580 * MPI Version: 01.02.04 2581 * 2582 * Version History 2583 * --------------- 2584 * 2585 * Date Version Description 2586 * -------- -------- ------------------------------------------------------ 2587 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 2588 * 05-24-00 00.10.02 Added SenseBufferLength to _MSG_SCSI_IO_REPLY. 2589 * 06-06-00 01.00.01 Update version number for 1.0 release. 2590 * 06-08-00 01.00.02 Added MPI_SCSI_RSP_INFO_ definitions. 2591 * 11-02-00 01.01.01 Original release for post 1.0 work. 2592 * 12-04-00 01.01.02 Added MPI_SCSIIO_CONTROL_NO_DISCONNECT. 2593 * 02-20-01 01.01.03 Started using MPI_POINTER. 2594 * 03-27-01 01.01.04 Added structure offset comments. 2595 * 04-10-01 01.01.05 Added new MsgFlag for MSG_SCSI_TASK_MGMT. 2596 * 08-08-01 01.02.01 Original release for v1.2 work. 2597 * 08-29-01 01.02.02 Added MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET. 2598 * Added MPI_SCSI_STATE_QUEUE_TAG_REJECTED for 2599 * MSG_SCSI_IO_REPLY. 2600 * 09-28-01 01.02.03 Added structures and defines for SCSI Enclosure 2601 * Processor messages. 2602 * 10-04-01 01.02.04 Added defines for SEP request Action field. 2603 * -------------------------------------------------------------------------- 2604 */ 2605 2606 #ifndef MPI_INIT_H 2607 #define MPI_INIT_H 2608 2609 2610 /***************************************************************************** 2611 * 2612 * S C S I I n i t i a t o r M e s s a g e s 2613 * 2614 *****************************************************************************/ 2615 2616 /****************************************************************************/ 2617 /* SCSI IO messages and assocaited structures */ 2618 /****************************************************************************/ 2619 2620 typedef struct _MSG_SCSI_IO_REQUEST 2621 { 2622 U8 TargetID; /* 00h */ 2623 U8 Bus; /* 01h */ 2624 U8 ChainOffset; /* 02h */ 2625 U8 Function; /* 03h */ 2626 U8 CDBLength; /* 04h */ 2627 U8 SenseBufferLength; /* 05h */ 2628 U8 Reserved; /* 06h */ 2629 U8 MsgFlags; /* 07h */ 2630 U32 MsgContext; /* 08h */ 2631 U8 LUN[8]; /* 0Ch */ 2632 U32 Control; /* 14h */ 2633 U8 CDB[16]; /* 18h */ 2634 U32 DataLength; /* 28h */ 2635 U32 SenseBufferLowAddr; /* 2Ch */ 2636 SGE_IO_UNION SGL; /* 30h */ 2637 } MSG_SCSI_IO_REQUEST, MPI_POINTER PTR_MSG_SCSI_IO_REQUEST, 2638 SCSIIORequest_t, MPI_POINTER pSCSIIORequest_t; 2639 2640 2641 /* SCSIO MsgFlags bits */ 2642 2643 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01) 2644 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00) 2645 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01) 2646 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02) 2647 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00) 2648 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02) 2649 2650 /* SCSIIO LUN fields */ 2651 2652 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 2653 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 2654 #define MPI_SCSIIO_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 2655 #define MPI_SCSIIO_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 2656 #define MPI_SCSIIO_LUN_LEVEL_1_WORD (0xFF00) 2657 #define MPI_SCSIIO_LUN_LEVEL_1_DWORD (0x0000FF00) 2658 2659 /* SCSIO Control bits */ 2660 2661 #define MPI_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 2662 #define MPI_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 2663 #define MPI_SCSIIO_CONTROL_WRITE (0x01000000) 2664 #define MPI_SCSIIO_CONTROL_READ (0x02000000) 2665 2666 #define MPI_SCSIIO_CONTROL_ADDCDBLEN_MASK (0x3C000000) 2667 #define MPI_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 2668 2669 #define MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 2670 #define MPI_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 2671 #define MPI_SCSIIO_CONTROL_HEADOFQ (0x00000100) 2672 #define MPI_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 2673 #define MPI_SCSIIO_CONTROL_ACAQ (0x00000400) 2674 #define MPI_SCSIIO_CONTROL_UNTAGGED (0x00000500) 2675 #define MPI_SCSIIO_CONTROL_NO_DISCONNECT (0x00000700) 2676 2677 #define MPI_SCSIIO_CONTROL_TASKMANAGE_MASK (0x00FF0000) 2678 #define MPI_SCSIIO_CONTROL_OBSOLETE (0x00800000) 2679 #define MPI_SCSIIO_CONTROL_CLEAR_ACA_RSV (0x00400000) 2680 #define MPI_SCSIIO_CONTROL_TARGET_RESET (0x00200000) 2681 #define MPI_SCSIIO_CONTROL_LUN_RESET_RSV (0x00100000) 2682 #define MPI_SCSIIO_CONTROL_RESERVED (0x00080000) 2683 #define MPI_SCSIIO_CONTROL_CLR_TASK_SET_RSV (0x00040000) 2684 #define MPI_SCSIIO_CONTROL_ABORT_TASK_SET (0x00020000) 2685 #define MPI_SCSIIO_CONTROL_RESERVED2 (0x00010000) 2686 2687 2688 /* SCSIIO reply structure */ 2689 typedef struct _MSG_SCSI_IO_REPLY 2690 { 2691 U8 TargetID; /* 00h */ 2692 U8 Bus; /* 01h */ 2693 U8 MsgLength; /* 02h */ 2694 U8 Function; /* 03h */ 2695 U8 CDBLength; /* 04h */ 2696 U8 SenseBufferLength; /* 05h */ 2697 U8 Reserved; /* 06h */ 2698 U8 MsgFlags; /* 07h */ 2699 U32 MsgContext; /* 08h */ 2700 U8 SCSIStatus; /* 0Ch */ 2701 U8 SCSIState; /* 0Dh */ 2702 U16 IOCStatus; /* 0Eh */ 2703 U32 IOCLogInfo; /* 10h */ 2704 U32 TransferCount; /* 14h */ 2705 U32 SenseCount; /* 18h */ 2706 U32 ResponseInfo; /* 1Ch */ 2707 } MSG_SCSI_IO_REPLY, MPI_POINTER PTR_MSG_SCSI_IO_REPLY, 2708 SCSIIOReply_t, MPI_POINTER pSCSIIOReply_t; 2709 2710 2711 /* SCSIIO Reply SCSIStatus values (SAM-2 status codes) */ 2712 2713 #define MPI_SCSI_STATUS_SUCCESS (0x00) 2714 #define MPI_SCSI_STATUS_CHECK_CONDITION (0x02) 2715 #define MPI_SCSI_STATUS_CONDITION_MET (0x04) 2716 #define MPI_SCSI_STATUS_BUSY (0x08) 2717 #define MPI_SCSI_STATUS_INTERMEDIATE (0x10) 2718 #define MPI_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14) 2719 #define MPI_SCSI_STATUS_RESERVATION_CONFLICT (0x18) 2720 #define MPI_SCSI_STATUS_COMMAND_TERMINATED (0x22) 2721 #define MPI_SCSI_STATUS_TASK_SET_FULL (0x28) 2722 #define MPI_SCSI_STATUS_ACA_ACTIVE (0x30) 2723 2724 2725 /* SCSIIO Reply SCSIState values */ 2726 2727 #define MPI_SCSI_STATE_AUTOSENSE_VALID (0x01) 2728 #define MPI_SCSI_STATE_AUTOSENSE_FAILED (0x02) 2729 #define MPI_SCSI_STATE_NO_SCSI_STATUS (0x04) 2730 #define MPI_SCSI_STATE_TERMINATED (0x08) 2731 #define MPI_SCSI_STATE_RESPONSE_INFO_VALID (0x10) 2732 #define MPI_SCSI_STATE_QUEUE_TAG_REJECTED (0x20) 2733 2734 /* SCSIIO Reply ResponseInfo values */ 2735 /* (FCP-1 RSP_CODE values and SPI-3 Packetized Failure codes) */ 2736 2737 #define MPI_SCSI_RSP_INFO_FUNCTION_COMPLETE (0x00000000) 2738 #define MPI_SCSI_RSP_INFO_FCP_BURST_LEN_ERROR (0x01000000) 2739 #define MPI_SCSI_RSP_INFO_CMND_FIELDS_INVALID (0x02000000) 2740 #define MPI_SCSI_RSP_INFO_FCP_DATA_RO_ERROR (0x03000000) 2741 #define MPI_SCSI_RSP_INFO_TASK_MGMT_UNSUPPORTED (0x04000000) 2742 #define MPI_SCSI_RSP_INFO_TASK_MGMT_FAILED (0x05000000) 2743 #define MPI_SCSI_RSP_INFO_SPI_LQ_INVALID_TYPE (0x06000000) 2744 2745 2746 /****************************************************************************/ 2747 /* SCSI Task Management messages */ 2748 /****************************************************************************/ 2749 2750 typedef struct _MSG_SCSI_TASK_MGMT 2751 { 2752 U8 TargetID; /* 00h */ 2753 U8 Bus; /* 01h */ 2754 U8 ChainOffset; /* 02h */ 2755 U8 Function; /* 03h */ 2756 U8 Reserved; /* 04h */ 2757 U8 TaskType; /* 05h */ 2758 U8 Reserved1; /* 06h */ 2759 U8 MsgFlags; /* 07h */ 2760 U32 MsgContext; /* 08h */ 2761 U8 LUN[8]; /* 0Ch */ 2762 U32 Reserved2[7]; /* 14h */ 2763 U32 TaskMsgContext; /* 30h */ 2764 } MSG_SCSI_TASK_MGMT, MPI_POINTER PTR_SCSI_TASK_MGMT, 2765 SCSITaskMgmt_t, MPI_POINTER pSCSITaskMgmt_t; 2766 2767 /* TaskType values */ 2768 2769 #define MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 2770 #define MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) 2771 #define MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 2772 #define MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS (0x04) 2773 #define MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 2774 2775 /* MsgFlags bits */ 2776 #define MPI_SCSITASKMGMT_MSGFLAGS_TARGET_RESET_OPTION (0x00) 2777 #define MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION (0x02) 2778 #define MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION (0x04) 2779 2780 /* SCSI Task Management Reply */ 2781 typedef struct _MSG_SCSI_TASK_MGMT_REPLY 2782 { 2783 U8 TargetID; /* 00h */ 2784 U8 Bus; /* 01h */ 2785 U8 MsgLength; /* 02h */ 2786 U8 Function; /* 03h */ 2787 U8 Reserved; /* 04h */ 2788 U8 TaskType; /* 05h */ 2789 U8 Reserved1; /* 06h */ 2790 U8 MsgFlags; /* 07h */ 2791 U32 MsgContext; /* 08h */ 2792 U8 Reserved2[2]; /* 0Ch */ 2793 U16 IOCStatus; /* 0Eh */ 2794 U32 IOCLogInfo; /* 10h */ 2795 U32 TerminationCount; /* 14h */ 2796 } MSG_SCSI_TASK_MGMT_REPLY, MPI_POINTER PTR_MSG_SCSI_TASK_MGMT_REPLY, 2797 SCSITaskMgmtReply_t, MPI_POINTER pSCSITaskMgmtReply_t; 2798 2799 2800 /****************************************************************************/ 2801 /* SCSI Enclosure Processor messages */ 2802 /****************************************************************************/ 2803 2804 typedef struct _MSG_SEP_REQUEST 2805 { 2806 U8 TargetID; /* 00h */ 2807 U8 Bus; /* 01h */ 2808 U8 ChainOffset; /* 02h */ 2809 U8 Function; /* 03h */ 2810 U8 Action; /* 04h */ 2811 U8 Reserved1; /* 05h */ 2812 U8 Reserved2; /* 06h */ 2813 U8 MsgFlags; /* 07h */ 2814 U32 MsgContext; /* 08h */ 2815 U32 SlotStatus; /* 0Ch */ 2816 } MSG_SEP_REQUEST, MPI_POINTER PTR_MSG_SEP_REQUEST, 2817 SEPRequest_t, MPI_POINTER pSEPRequest_t; 2818 2819 /* Action defines */ 2820 #define MPI_SEP_REQ_ACTION_WRITE_STATUS (0x00) 2821 #define MPI_SEP_REQ_ACTION_READ_STATUS (0x01) 2822 2823 /* SlotStatus bits for MSG_SEP_REQUEST */ 2824 #define MPI_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001) 2825 #define MPI_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002) 2826 #define MPI_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004) 2827 #define MPI_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) 2828 #define MPI_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) 2829 #define MPI_SEP_REQ_SLOTSTATUS_PARITY_CHECK (0x00000020) 2830 #define MPI_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040) 2831 #define MPI_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080) 2832 #define MPI_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100) 2833 #define MPI_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200) 2834 #define MPI_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) 2835 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000) 2836 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_INSERT (0x00080000) 2837 #define MPI_SEP_REQ_SLOTSTATUS_DO_NOT_MOVE (0x00400000) 2838 #define MPI_SEP_REQ_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) 2839 #define MPI_SEP_REQ_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) 2840 #define MPI_SEP_REQ_SLOTSTATUS_DEV_OFF (0x10000000) 2841 #define MPI_SEP_REQ_SLOTSTATUS_SWAP_RESET (0x80000000) 2842 2843 2844 typedef struct _MSG_SEP_REPLY 2845 { 2846 U8 TargetID; /* 00h */ 2847 U8 Bus; /* 01h */ 2848 U8 MsgLength; /* 02h */ 2849 U8 Function; /* 03h */ 2850 U8 Action; /* 04h */ 2851 U8 Reserved1; /* 05h */ 2852 U8 Reserved2; /* 06h */ 2853 U8 MsgFlags; /* 07h */ 2854 U32 MsgContext; /* 08h */ 2855 U16 Reserved3; /* 0Ch */ 2856 U16 IOCStatus; /* 0Eh */ 2857 U32 IOCLogInfo; /* 10h */ 2858 U32 SlotStatus; /* 14h */ 2859 } MSG_SEP_REPLY, MPI_POINTER PTR_MSG_SEP_REPLY, 2860 SEPReply_t, MPI_POINTER pSEPReply_t; 2861 2862 /* SlotStatus bits for MSG_SEP_REPLY */ 2863 #define MPI_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001) 2864 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002) 2865 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004) 2866 #define MPI_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) 2867 #define MPI_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) 2868 #define MPI_SEP_REPLY_SLOTSTATUS_PARITY_CHECK (0x00000020) 2869 #define MPI_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040) 2870 #define MPI_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080) 2871 #define MPI_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100) 2872 #define MPI_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200) 2873 #define MPI_SEP_REPLY_SLOTSTATUS_REPORT (0x00010000) 2874 #define MPI_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) 2875 #define MPI_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000) 2876 #define MPI_SEP_REPLY_SLOTSTATUS_INSERT_READY (0x00080000) 2877 #define MPI_SEP_REPLY_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 2878 #define MPI_SEP_REPLY_SLOTSTATUS_B_BYPASS_ENABLED (0x01000000) 2879 #define MPI_SEP_REPLY_SLOTSTATUS_A_BYPASS_ENABLED (0x02000000) 2880 #define MPI_SEP_REPLY_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) 2881 #define MPI_SEP_REPLY_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) 2882 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x10000000) 2883 #define MPI_SEP_REPLY_SLOTSTATUS_FAULT_SENSED (0x40000000) 2884 #define MPI_SEP_REPLY_SLOTSTATUS_SWAPPED (0x80000000) 2885 2886 #endif 2887 2888 /* 2889 * Copyright (c) 2000, 2001 by LSI Logic Corporation 2890 * 2891 * Redistribution and use in source and binary forms, with or without 2892 * modification, are permitted provided that the following conditions 2893 * are met: 2894 * 1. Redistributions of source code must retain the above copyright 2895 * notice immediately at the beginning of the file, without modification, 2896 * this list of conditions, and the following disclaimer. 2897 * 2. The name of the author may not be used to endorse or promote products 2898 * derived from this software without specific prior written permission. 2899 * 2900 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2901 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2902 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2903 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2904 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2905 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2906 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2907 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2908 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2909 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2910 * SUCH DAMAGE. 2911 * 2912 * 2913 * Name: MPI_IOC.H 2914 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 2915 * Creation Date: August 11, 2000 2916 * 2917 * MPI Version: 01.02.04 2918 * 2919 * Version History 2920 * --------------- 2921 * 2922 * Date Version Description 2923 * -------- -------- ------------------------------------------------------ 2924 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 2925 * 05-24-00 00.10.02 Added _MSG_IOC_INIT_REPLY structure. 2926 * 06-06-00 01.00.01 Added CurReplyFrameSize field to _MSG_IOC_FACTS_REPLY. 2927 * 06-12-00 01.00.02 Added _MSG_PORT_ENABLE_REPLY structure. 2928 * Added _MSG_EVENT_ACK_REPLY structure. 2929 * Added _MSG_FW_DOWNLOAD_REPLY structure. 2930 * Added _MSG_TOOLBOX_REPLY structure. 2931 * 06-30-00 01.00.03 Added MaxLanBuckets to _PORT_FACT_REPLY structure. 2932 * 07-27-00 01.00.04 Added _EVENT_DATA structure definitions for _SCSI, 2933 * _LINK_STATUS, _LOOP_STATE and _LOGOUT. 2934 * 08-11-00 01.00.05 Switched positions of MsgLength and Function fields in 2935 * _MSG_EVENT_ACK_REPLY structure to match specification. 2936 * 11-02-00 01.01.01 Original release for post 1.0 work. 2937 * Added a value for Manufacturer to WhoInit. 2938 * 12-04-00 01.01.02 Modified IOCFacts reply, added FWUpload messages, and 2939 * removed toolbox message. 2940 * 01-09-01 01.01.03 Added event enabled and disabled defines. 2941 * Added structures for FwHeader and DataHeader. 2942 * Added ImageType to FwUpload reply. 2943 * 02-20-01 01.01.04 Started using MPI_POINTER. 2944 * 02-27-01 01.01.05 Added event for RAID status change and its event data. 2945 * Added IocNumber field to MSG_IOC_FACTS_REPLY. 2946 * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER. 2947 * Added structure offset comments. 2948 * 04-09-01 01.01.07 Added structure EVENT_DATA_EVENT_CHANGE. 2949 * 08-08-01 01.02.01 Original release for v1.2 work. 2950 * New format for FWVersion and ProductId in 2951 * MSG_IOC_FACTS_REPLY and MPI_FW_HEADER. 2952 * 08-31-01 01.02.02 Addded event MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE and 2953 * related structure and defines. 2954 * Added event MPI_EVENT_ON_BUS_TIMER_EXPIRED. 2955 * Added MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE. 2956 * Replaced a reserved field in MSG_IOC_FACTS_REPLY with 2957 * IOCExceptions and changed DataImageSize to reserved. 2958 * Added MPI_FW_DOWNLOAD_ITYPE_NVSTORE_DATA and 2959 * MPI_FW_UPLOAD_ITYPE_NVDATA. 2960 * 09-28-01 01.02.03 Modified Event Data for Integrated RAID. 2961 * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field. 2962 * -------------------------------------------------------------------------- 2963 */ 2964 2965 #ifndef MPI_IOC_H 2966 #define MPI_IOC_H 2967 2968 2969 /***************************************************************************** 2970 * 2971 * I O C M e s s a g e s 2972 * 2973 *****************************************************************************/ 2974 2975 /****************************************************************************/ 2976 /* IOCInit message */ 2977 /****************************************************************************/ 2978 2979 typedef struct _MSG_IOC_INIT 2980 { 2981 U8 WhoInit; /* 00h */ 2982 U8 Reserved; /* 01h */ 2983 U8 ChainOffset; /* 02h */ 2984 U8 Function; /* 03h */ 2985 U8 Flags; /* 04h */ 2986 U8 MaxDevices; /* 05h */ 2987 U8 MaxBuses; /* 06h */ 2988 U8 MsgFlags; /* 07h */ 2989 U32 MsgContext; /* 08h */ 2990 U16 ReplyFrameSize; /* 0Ch */ 2991 U8 Reserved1[2]; /* 0Eh */ 2992 U32 HostMfaHighAddr; /* 10h */ 2993 U32 SenseBufferHighAddr; /* 14h */ 2994 } MSG_IOC_INIT, MPI_POINTER PTR_MSG_IOC_INIT, 2995 IOCInit_t, MPI_POINTER pIOCInit_t; 2996 2997 /* WhoInit values */ 2998 #define MPI_WHOINIT_NO_ONE (0x00) 2999 #define MPI_WHOINIT_SYSTEM_BIOS (0x01) 3000 #define MPI_WHOINIT_ROM_BIOS (0x02) 3001 #define MPI_WHOINIT_PCI_PEER (0x03) 3002 #define MPI_WHOINIT_HOST_DRIVER (0x04) 3003 #define MPI_WHOINIT_MANUFACTURER (0x05) 3004 3005 /* Flags values */ 3006 #define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE (0x01) 3007 3008 typedef struct _MSG_IOC_INIT_REPLY 3009 { 3010 U8 WhoInit; /* 00h */ 3011 U8 Reserved; /* 01h */ 3012 U8 MsgLength; /* 02h */ 3013 U8 Function; /* 03h */ 3014 U8 Flags; /* 04h */ 3015 U8 MaxDevices; /* 05h */ 3016 U8 MaxBuses; /* 06h */ 3017 U8 MsgFlags; /* 07h */ 3018 U32 MsgContext; /* 08h */ 3019 U16 Reserved2; /* 0Ch */ 3020 U16 IOCStatus; /* 0Eh */ 3021 U32 IOCLogInfo; /* 10h */ 3022 } MSG_IOC_INIT_REPLY, MPI_POINTER PTR_MSG_IOC_INIT_REPLY, 3023 IOCInitReply_t, MPI_POINTER pIOCInitReply_t; 3024 3025 3026 3027 /****************************************************************************/ 3028 /* IOC Facts message */ 3029 /****************************************************************************/ 3030 3031 typedef struct _MSG_IOC_FACTS 3032 { 3033 U8 Reserved[2]; /* 00h */ 3034 U8 ChainOffset; /* 01h */ 3035 U8 Function; /* 02h */ 3036 U8 Reserved1[3]; /* 03h */ 3037 U8 MsgFlags; /* 04h */ 3038 U32 MsgContext; /* 08h */ 3039 } MSG_IOC_FACTS, MPI_POINTER PTR_IOC_FACTS, 3040 IOCFacts_t, MPI_POINTER pIOCFacts_t; 3041 3042 typedef struct _MPI_FW_VERSION_STRUCT 3043 { 3044 U8 Dev; /* 00h */ 3045 U8 Unit; /* 01h */ 3046 U8 Minor; /* 02h */ 3047 U8 Major; /* 03h */ 3048 } MPI_FW_VERSION_STRUCT; 3049 3050 typedef union _MPI_FW_VERSION 3051 { 3052 MPI_FW_VERSION_STRUCT Struct; 3053 U32 Word; 3054 } MPI_FW_VERSION; 3055 3056 /* IOC Facts Reply */ 3057 typedef struct _MSG_IOC_FACTS_REPLY 3058 { 3059 U16 MsgVersion; /* 00h */ 3060 U8 MsgLength; /* 02h */ 3061 U8 Function; /* 03h */ 3062 U16 Reserved; /* 04h */ 3063 U8 IOCNumber; /* 06h */ 3064 U8 MsgFlags; /* 07h */ 3065 U32 MsgContext; /* 08h */ 3066 U16 IOCExceptions; /* 0Ch */ 3067 U16 IOCStatus; /* 0Eh */ 3068 U32 IOCLogInfo; /* 10h */ 3069 U8 MaxChainDepth; /* 14h */ 3070 U8 WhoInit; /* 15h */ 3071 U8 BlockSize; /* 16h */ 3072 U8 Flags; /* 17h */ 3073 U16 ReplyQueueDepth; /* 18h */ 3074 U16 RequestFrameSize; /* 1Ah */ 3075 U16 Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */ 3076 U16 ProductID; /* 1Eh */ 3077 U32 CurrentHostMfaHighAddr; /* 20h */ 3078 U16 GlobalCredits; /* 24h */ 3079 U8 NumberOfPorts; /* 26h */ 3080 U8 EventState; /* 27h */ 3081 U32 CurrentSenseBufferHighAddr; /* 28h */ 3082 U16 CurReplyFrameSize; /* 2Ch */ 3083 U8 MaxDevices; /* 2Eh */ 3084 U8 MaxBuses; /* 2Fh */ 3085 U32 FWImageSize; /* 30h */ 3086 U32 Reserved4; /* 34h */ 3087 MPI_FW_VERSION FWVersion; /* 38h */ 3088 } MSG_IOC_FACTS_REPLY, MPI_POINTER PTR_MSG_IOC_FACTS_REPLY, 3089 IOCFactsReply_t, MPI_POINTER pIOCFactsReply_t; 3090 3091 #define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 3092 #define MPI_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 3093 3094 #define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 3095 3096 #define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (0x01) 3097 3098 #define MPI_IOCFACTS_EVENTSTATE_DISABLED (0x00) 3099 #define MPI_IOCFACTS_EVENTSTATE_ENABLED (0x01) 3100 3101 3102 3103 /***************************************************************************** 3104 * 3105 * P o r t M e s s a g e s 3106 * 3107 *****************************************************************************/ 3108 3109 /****************************************************************************/ 3110 /* Port Facts message and Reply */ 3111 /****************************************************************************/ 3112 3113 typedef struct _MSG_PORT_FACTS 3114 { 3115 U8 Reserved[2]; /* 00h */ 3116 U8 ChainOffset; /* 02h */ 3117 U8 Function; /* 03h */ 3118 U8 Reserved1[2]; /* 04h */ 3119 U8 PortNumber; /* 06h */ 3120 U8 MsgFlags; /* 07h */ 3121 U32 MsgContext; /* 08h */ 3122 } MSG_PORT_FACTS, MPI_POINTER PTR_MSG_PORT_FACTS, 3123 PortFacts_t, MPI_POINTER pPortFacts_t; 3124 3125 typedef struct _MSG_PORT_FACTS_REPLY 3126 { 3127 U16 Reserved; /* 00h */ 3128 U8 MsgLength; /* 02h */ 3129 U8 Function; /* 03h */ 3130 U16 Reserved1; /* 04h */ 3131 U8 PortNumber; /* 06h */ 3132 U8 MsgFlags; /* 07h */ 3133 U32 MsgContext; /* 08h */ 3134 U16 Reserved2; /* 0Ch */ 3135 U16 IOCStatus; /* 0Eh */ 3136 U32 IOCLogInfo; /* 10h */ 3137 U8 Reserved3; /* 14h */ 3138 U8 PortType; /* 15h */ 3139 U16 MaxDevices; /* 16h */ 3140 U16 PortSCSIID; /* 18h */ 3141 U16 ProtocolFlags; /* 1Ah */ 3142 U16 MaxPostedCmdBuffers; /* 1Ch */ 3143 U16 MaxPersistentIDs; /* 1Eh */ 3144 U16 MaxLanBuckets; /* 20h */ 3145 U16 Reserved4; /* 22h */ 3146 U32 Reserved5; /* 24h */ 3147 } MSG_PORT_FACTS_REPLY, MPI_POINTER PTR_MSG_PORT_FACTS_REPLY, 3148 PortFactsReply_t, MPI_POINTER pPortFactsReply_t; 3149 3150 3151 /* PortTypes values */ 3152 3153 #define MPI_PORTFACTS_PORTTYPE_INACTIVE (0x00) 3154 #define MPI_PORTFACTS_PORTTYPE_SCSI (0x01) 3155 #define MPI_PORTFACTS_PORTTYPE_FC (0x10) 3156 3157 /* ProtocolFlags values */ 3158 3159 #define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (0x01) 3160 #define MPI_PORTFACTS_PROTOCOL_LAN (0x02) 3161 #define MPI_PORTFACTS_PROTOCOL_TARGET (0x04) 3162 #define MPI_PORTFACTS_PROTOCOL_INITIATOR (0x08) 3163 3164 3165 /****************************************************************************/ 3166 /* Port Enable Message */ 3167 /****************************************************************************/ 3168 3169 typedef struct _MSG_PORT_ENABLE 3170 { 3171 U8 Reserved[2]; /* 00h */ 3172 U8 ChainOffset; /* 02h */ 3173 U8 Function; /* 03h */ 3174 U8 Reserved1[2]; /* 04h */ 3175 U8 PortNumber; /* 06h */ 3176 U8 MsgFlags; /* 07h */ 3177 U32 MsgContext; /* 08h */ 3178 } MSG_PORT_ENABLE, MPI_POINTER PTR_MSG_PORT_ENABLE, 3179 PortEnable_t, MPI_POINTER pPortEnable_t; 3180 3181 typedef struct _MSG_PORT_ENABLE_REPLY 3182 { 3183 U8 Reserved[2]; /* 00h */ 3184 U8 MsgLength; /* 02h */ 3185 U8 Function; /* 03h */ 3186 U8 Reserved1[2]; /* 04h */ 3187 U8 PortNumber; /* 05h */ 3188 U8 MsgFlags; /* 07h */ 3189 U32 MsgContext; /* 08h */ 3190 U16 Reserved2; /* 0Ch */ 3191 U16 IOCStatus; /* 0Eh */ 3192 U32 IOCLogInfo; /* 10h */ 3193 } MSG_PORT_ENABLE_REPLY, MPI_POINTER PTR_MSG_PORT_ENABLE_REPLY, 3194 PortEnableReply_t, MPI_POINTER pPortEnableReply_t; 3195 3196 3197 /***************************************************************************** 3198 * 3199 * E v e n t M e s s a g e s 3200 * 3201 *****************************************************************************/ 3202 3203 /****************************************************************************/ 3204 /* Event Notification messages */ 3205 /****************************************************************************/ 3206 3207 typedef struct _MSG_EVENT_NOTIFY 3208 { 3209 U8 Switch; /* 00h */ 3210 U8 Reserved; /* 01h */ 3211 U8 ChainOffset; /* 02h */ 3212 U8 Function; /* 03h */ 3213 U8 Reserved1[3]; /* 04h */ 3214 U8 MsgFlags; /* 07h */ 3215 U32 MsgContext; /* 08h */ 3216 } MSG_EVENT_NOTIFY, MPI_POINTER PTR_MSG_EVENT_NOTIFY, 3217 EventNotification_t, MPI_POINTER pEventNotification_t; 3218 3219 /* Event Notification Reply */ 3220 3221 typedef struct _MSG_EVENT_NOTIFY_REPLY 3222 { 3223 U16 EventDataLength; /* 00h */ 3224 U8 MsgLength; /* 02h */ 3225 U8 Function; /* 03h */ 3226 U8 Reserved1[2]; /* 04h */ 3227 U8 AckRequired; /* 06h */ 3228 U8 MsgFlags; /* 07h */ 3229 U32 MsgContext; /* 08h */ 3230 U8 Reserved2[2]; /* 0Ch */ 3231 U16 IOCStatus; /* 0Eh */ 3232 U32 IOCLogInfo; /* 10h */ 3233 U32 Event; /* 14h */ 3234 U32 EventContext; /* 18h */ 3235 U32 Data[1]; /* 1Ch */ 3236 } MSG_EVENT_NOTIFY_REPLY, MPI_POINTER PTR_MSG_EVENT_NOTIFY_REPLY, 3237 EventNotificationReply_t, MPI_POINTER pEventNotificationReply_t; 3238 3239 /* Event Acknowledge */ 3240 3241 typedef struct _MSG_EVENT_ACK 3242 { 3243 U8 Reserved[2]; /* 00h */ 3244 U8 ChainOffset; /* 02h */ 3245 U8 Function; /* 03h */ 3246 U8 Reserved1[3]; /* 04h */ 3247 U8 MsgFlags; /* 07h */ 3248 U32 MsgContext; /* 08h */ 3249 U32 Event; /* 0Ch */ 3250 U32 EventContext; /* 10h */ 3251 } MSG_EVENT_ACK, MPI_POINTER PTR_MSG_EVENT_ACK, 3252 EventAck_t, MPI_POINTER pEventAck_t; 3253 3254 typedef struct _MSG_EVENT_ACK_REPLY 3255 { 3256 U8 Reserved[2]; /* 00h */ 3257 U8 MsgLength; /* 02h */ 3258 U8 Function; /* 03h */ 3259 U8 Reserved1[3]; /* 04h */ 3260 U8 MsgFlags; /* 07h */ 3261 U32 MsgContext; /* 08h */ 3262 U16 Reserved2; /* 0Ch */ 3263 U16 IOCStatus; /* 0Eh */ 3264 U32 IOCLogInfo; /* 10h */ 3265 } MSG_EVENT_ACK_REPLY, MPI_POINTER PTR_MSG_EVENT_ACK_REPLY, 3266 EventAckReply_t, MPI_POINTER pEventAckReply_t; 3267 3268 /* Switch */ 3269 3270 #define MPI_EVENT_NOTIFICATION_SWITCH_OFF (0x00) 3271 #define MPI_EVENT_NOTIFICATION_SWITCH_ON (0x01) 3272 3273 /* Event */ 3274 3275 #define MPI_EVENT_NONE (0x00000000) 3276 #define MPI_EVENT_LOG_DATA (0x00000001) 3277 #define MPI_EVENT_STATE_CHANGE (0x00000002) 3278 #define MPI_EVENT_UNIT_ATTENTION (0x00000003) 3279 #define MPI_EVENT_IOC_BUS_RESET (0x00000004) 3280 #define MPI_EVENT_EXT_BUS_RESET (0x00000005) 3281 #define MPI_EVENT_RESCAN (0x00000006) 3282 #define MPI_EVENT_LINK_STATUS_CHANGE (0x00000007) 3283 #define MPI_EVENT_LOOP_STATE_CHANGE (0x00000008) 3284 #define MPI_EVENT_LOGOUT (0x00000009) 3285 #define MPI_EVENT_EVENT_CHANGE (0x0000000A) 3286 #define MPI_EVENT_INTEGRATED_RAID (0x0000000B) 3287 #define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE (0x0000000C) 3288 #define MPI_EVENT_ON_BUS_TIMER_EXPIRED (0x0000000D) 3289 3290 /* AckRequired field values */ 3291 3292 #define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 3293 #define MPI_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 3294 3295 /* EventChange Event data */ 3296 3297 typedef struct _EVENT_DATA_EVENT_CHANGE 3298 { 3299 U8 EventState; /* 00h */ 3300 U8 Reserved; /* 01h */ 3301 U16 Reserved1; /* 02h */ 3302 } EVENT_DATA_EVENT_CHANGE, MPI_POINTER PTR_EVENT_DATA_EVENT_CHANGE, 3303 EventDataEventChange_t, MPI_POINTER pEventDataEventChange_t; 3304 3305 /* SCSI Event data for Port, Bus and Device forms */ 3306 3307 typedef struct _EVENT_DATA_SCSI 3308 { 3309 U8 TargetID; /* 00h */ 3310 U8 BusPort; /* 01h */ 3311 U16 Reserved; /* 02h */ 3312 } EVENT_DATA_SCSI, MPI_POINTER PTR_EVENT_DATA_SCSI, 3313 EventDataScsi_t, MPI_POINTER pEventDataScsi_t; 3314 3315 /* SCSI Device Status Change Event data */ 3316 3317 typedef struct _EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE 3318 { 3319 U8 TargetID; /* 00h */ 3320 U8 Bus; /* 01h */ 3321 U8 ReasonCode; /* 02h */ 3322 U8 LUN; /* 03h */ 3323 U8 ASC; /* 04h */ 3324 U8 ASCQ; /* 05h */ 3325 U16 Reserved; /* 06h */ 3326 } EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 3327 MPI_POINTER PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 3328 MpiEventDataScsiDeviceStatusChange_t, 3329 MPI_POINTER pMpiEventDataScsiDeviceStatusChange_t; 3330 3331 /* MPI SCSI Device Status Change Event data ReasonCode values */ 3332 #define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED (0x03) 3333 #define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING (0x04) 3334 #define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA (0x05) 3335 3336 /* MPI Link Status Change Event data */ 3337 3338 typedef struct _EVENT_DATA_LINK_STATUS 3339 { 3340 U8 State; /* 00h */ 3341 U8 Reserved; /* 01h */ 3342 U16 Reserved1; /* 02h */ 3343 U8 Reserved2; /* 04h */ 3344 U8 Port; /* 05h */ 3345 U16 Reserved3; /* 06h */ 3346 } EVENT_DATA_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_LINK_STATUS, 3347 EventDataLinkStatus_t, MPI_POINTER pEventDataLinkStatus_t; 3348 3349 #define MPI_EVENT_LINK_STATUS_FAILURE (0x00000000) 3350 #define MPI_EVENT_LINK_STATUS_ACTIVE (0x00000001) 3351 3352 /* MPI Loop State Change Event data */ 3353 3354 typedef struct _EVENT_DATA_LOOP_STATE 3355 { 3356 U8 Character4; /* 00h */ 3357 U8 Character3; /* 01h */ 3358 U8 Type; /* 02h */ 3359 U8 Reserved; /* 03h */ 3360 U8 Reserved1; /* 04h */ 3361 U8 Port; /* 05h */ 3362 U16 Reserved2; /* 06h */ 3363 } EVENT_DATA_LOOP_STATE, MPI_POINTER PTR_EVENT_DATA_LOOP_STATE, 3364 EventDataLoopState_t, MPI_POINTER pEventDataLoopState_t; 3365 3366 #define MPI_EVENT_LOOP_STATE_CHANGE_LIP (0x0001) 3367 #define MPI_EVENT_LOOP_STATE_CHANGE_LPE (0x0002) 3368 #define MPI_EVENT_LOOP_STATE_CHANGE_LPB (0x0003) 3369 3370 /* MPI LOGOUT Event data */ 3371 3372 typedef struct _EVENT_DATA_LOGOUT 3373 { 3374 U32 NPortID; /* 00h */ 3375 U8 Reserved; /* 04h */ 3376 U8 Port; /* 05h */ 3377 U16 Reserved1; /* 06h */ 3378 } EVENT_DATA_LOGOUT, MPI_POINTER PTR_EVENT_DATA_LOGOUT, 3379 EventDataLogout_t, MPI_POINTER pEventDataLogout_t; 3380 3381 /* MPI Integrated RAID Event data */ 3382 3383 typedef struct _EVENT_DATA_RAID 3384 { 3385 U8 VolumeID; /* 00h */ 3386 U8 VolumeBus; /* 01h */ 3387 U8 ReasonCode; /* 02h */ 3388 U8 PhysDiskNum; /* 03h */ 3389 U8 ASC; /* 04h */ 3390 U8 ASCQ; /* 05h */ 3391 U16 Reserved; /* 06h */ 3392 U32 SettingsStatus; /* 08h */ 3393 } EVENT_DATA_RAID, MPI_POINTER PTR_EVENT_DATA_RAID, 3394 MpiEventDataRaid_t, MPI_POINTER pMpiEventDataRaid_t; 3395 3396 /* MPI Integrated RAID Event data ReasonCode values */ 3397 #define MPI_EVENT_RAID_RC_VOLUME_CREATED (0x00) 3398 #define MPI_EVENT_RAID_RC_VOLUME_DELETED (0x01) 3399 #define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED (0x02) 3400 #define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED (0x03) 3401 #define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED (0x04) 3402 #define MPI_EVENT_RAID_RC_PHYSDISK_CREATED (0x05) 3403 #define MPI_EVENT_RAID_RC_PHYSDISK_DELETED (0x06) 3404 #define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED (0x07) 3405 #define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED (0x08) 3406 #define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED (0x09) 3407 #define MPI_EVENT_RAID_RC_SMART_DATA (0x0A) 3408 #define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED (0x0B) 3409 3410 3411 /***************************************************************************** 3412 * 3413 * F i r m w a r e L o a d M e s s a g e s 3414 * 3415 *****************************************************************************/ 3416 3417 /****************************************************************************/ 3418 /* Firmware Download message and associated structures */ 3419 /****************************************************************************/ 3420 3421 typedef struct _MSG_FW_DOWNLOAD 3422 { 3423 U8 ImageType; /* 00h */ 3424 U8 Reserved; /* 01h */ 3425 U8 ChainOffset; /* 02h */ 3426 U8 Function; /* 03h */ 3427 U8 Reserved1[3]; /* 04h */ 3428 U8 MsgFlags; /* 07h */ 3429 U32 MsgContext; /* 08h */ 3430 SGE_MPI_UNION SGL; /* 0Ch */ 3431 } MSG_FW_DOWNLOAD, MPI_POINTER PTR_MSG_FW_DOWNLOAD, 3432 FWDownload_t, MPI_POINTER pFWDownload_t; 3433 3434 #define MPI_FW_DOWNLOAD_ITYPE_RESERVED (0x00) 3435 #define MPI_FW_DOWNLOAD_ITYPE_FW (0x01) 3436 #define MPI_FW_DOWNLOAD_ITYPE_BIOS (0x02) 3437 #define MPI_FW_DOWNLOAD_ITYPE_NVDATA (0x03) 3438 3439 3440 typedef struct _FWDownloadTCSGE 3441 { 3442 U8 Reserved; /* 00h */ 3443 U8 ContextSize; /* 01h */ 3444 U8 DetailsLength; /* 02h */ 3445 U8 Flags; /* 03h */ 3446 U32 Reserved_0100_Checksum; /* 04h */ /* obsolete Checksum */ 3447 U32 ImageOffset; /* 08h */ 3448 U32 ImageSize; /* 0Ch */ 3449 } FW_DOWNLOAD_TCSGE, MPI_POINTER PTR_FW_DOWNLOAD_TCSGE, 3450 FWDownloadTCSGE_t, MPI_POINTER pFWDownloadTCSGE_t; 3451 3452 /* Firmware Download reply */ 3453 typedef struct _MSG_FW_DOWNLOAD_REPLY 3454 { 3455 U8 ImageType; /* 00h */ 3456 U8 Reserved; /* 01h */ 3457 U8 MsgLength; /* 02h */ 3458 U8 Function; /* 03h */ 3459 U8 Reserved1[3]; /* 04h */ 3460 U8 MsgFlags; /* 07h */ 3461 U32 MsgContext; /* 08h */ 3462 U16 Reserved2; /* 0Ch */ 3463 U16 IOCStatus; /* 0Eh */ 3464 U32 IOCLogInfo; /* 10h */ 3465 } MSG_FW_DOWNLOAD_REPLY, MPI_POINTER PTR_MSG_FW_DOWNLOAD_REPLY, 3466 FWDownloadReply_t, MPI_POINTER pFWDownloadReply_t; 3467 3468 3469 /****************************************************************************/ 3470 /* Firmware Upload message and associated structures */ 3471 /****************************************************************************/ 3472 3473 typedef struct _MSG_FW_UPLOAD 3474 { 3475 U8 ImageType; /* 00h */ 3476 U8 Reserved; /* 01h */ 3477 U8 ChainOffset; /* 02h */ 3478 U8 Function; /* 03h */ 3479 U8 Reserved1[3]; /* 04h */ 3480 U8 MsgFlags; /* 07h */ 3481 U32 MsgContext; /* 08h */ 3482 SGE_MPI_UNION SGL; /* 0Ch */ 3483 } MSG_FW_UPLOAD, MPI_POINTER PTR_MSG_FW_UPLOAD, 3484 FWUpload_t, MPI_POINTER pFWUpload_t; 3485 3486 #define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM (0x00) 3487 #define MPI_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 3488 #define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 3489 #define MPI_FW_UPLOAD_ITYPE_NVDATA (0x03) 3490 3491 typedef struct _FWUploadTCSGE 3492 { 3493 U8 Reserved; /* 00h */ 3494 U8 ContextSize; /* 01h */ 3495 U8 DetailsLength; /* 02h */ 3496 U8 Flags; /* 03h */ 3497 U32 Reserved1; /* 04h */ 3498 U32 ImageOffset; /* 08h */ 3499 U32 ImageSize; /* 0Ch */ 3500 } FW_UPLOAD_TCSGE, MPI_POINTER PTR_FW_UPLOAD_TCSGE, 3501 FWUploadTCSGE_t, MPI_POINTER pFWUploadTCSGE_t; 3502 3503 /* Firmware Upload reply */ 3504 typedef struct _MSG_FW_UPLOAD_REPLY 3505 { 3506 U8 ImageType; /* 00h */ 3507 U8 Reserved; /* 01h */ 3508 U8 MsgLength; /* 02h */ 3509 U8 Function; /* 03h */ 3510 U8 Reserved1[3]; /* 04h */ 3511 U8 MsgFlags; /* 07h */ 3512 U32 MsgContext; /* 08h */ 3513 U16 Reserved2; /* 0Ch */ 3514 U16 IOCStatus; /* 0Eh */ 3515 U32 IOCLogInfo; /* 10h */ 3516 U32 ActualImageSize; /* 14h */ 3517 } MSG_FW_UPLOAD_REPLY, MPI_POINTER PTR_MSG_FW_UPLOAD_REPLY, 3518 FWUploadReply_t, MPI_POINTER pFWUploadReply_t; 3519 3520 3521 typedef struct _MPI_FW_HEADER 3522 { 3523 U32 ArmBranchInstruction0; /* 00h */ 3524 U32 Signature0; /* 04h */ 3525 U32 Signature1; /* 08h */ 3526 U32 Signature2; /* 0Ch */ 3527 U32 ArmBranchInstruction1; /* 10h */ 3528 U32 ArmBranchInstruction2; /* 14h */ 3529 U32 Reserved; /* 18h */ 3530 U32 Checksum; /* 1Ch */ 3531 U16 VendorId; /* 20h */ 3532 U16 ProductId; /* 22h */ 3533 MPI_FW_VERSION FWVersion; /* 24h */ 3534 U32 SeqCodeVersion; /* 28h */ 3535 U32 ImageSize; /* 2Ch */ 3536 U32 NextImageHeaderOffset; /* 30h */ 3537 U32 LoadStartAddress; /* 34h */ 3538 U32 IopResetVectorValue; /* 38h */ 3539 U32 IopResetRegAddr; /* 3Ch */ 3540 U32 VersionNameWhat; /* 40h */ 3541 U8 VersionName[32]; /* 44h */ 3542 U32 VendorNameWhat; /* 64h */ 3543 U8 VendorName[32]; /* 68h */ 3544 } MPI_FW_HEADER, MPI_POINTER PTR_MPI_FW_HEADER, 3545 MpiFwHeader_t, MPI_POINTER pMpiFwHeader_t; 3546 3547 #define MPI_FW_HEADER_WHAT_SIGNATURE (0x29232840) 3548 3549 /* defines for using the ProductId field */ 3550 #define MPI_FW_HEADER_PID_TYPE_MASK (0xF000) 3551 #define MPI_FW_HEADER_PID_TYPE_SCSI (0x0000) 3552 #define MPI_FW_HEADER_PID_TYPE_FC (0x1000) 3553 3554 #define MPI_FW_HEADER_PID_PROD_MASK (0x0F00) 3555 #define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI (0x0100) 3556 #define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 3557 #define MPI_FW_HEADER_PID_PROD_TARGET_SCSI (0x0300) 3558 #define MPI_FW_HEADER_PID_PROD_IM_SCSI (0x0400) 3559 #define MPI_FW_HEADER_PID_PROD_IS_SCSI (0x0500) 3560 #define MPI_FW_HEADER_PID_PROD_CTX_SCSI (0x0600) 3561 3562 #define MPI_FW_HEADER_PID_FAMILY_MASK (0x00FF) 3563 #define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI (0x0001) 3564 #define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI (0x0002) 3565 #define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI (0x0003) 3566 #define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI (0x0004) 3567 #define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI (0x0005) 3568 #define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI (0x0006) 3569 #define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI (0x0007) 3570 #define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI (0x0008) 3571 #define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI (0x0009) 3572 #define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI (0x000A) 3573 #define MPI_FW_HEADER_PID_FAMILY_909_FC (0x0000) 3574 #define MPI_FW_HEADER_PID_FAMILY_919_FC (0x0001) 3575 #define MPI_FW_HEADER_PID_FAMILY_919X_FC (0x0002) 3576 3577 typedef struct _MPI_EXT_IMAGE_HEADER 3578 { 3579 U8 ImageType; /* 00h */ 3580 U8 Reserved; /* 01h */ 3581 U16 Reserved1; /* 02h */ 3582 U32 Checksum; /* 04h */ 3583 U32 ImageSize; /* 08h */ 3584 U32 NextImageHeaderOffset; /* 0Ch */ 3585 U32 LoadStartAddress; /* 10h */ 3586 U32 Reserved2; /* 14h */ 3587 } MPI_EXT_IMAGE_HEADER, MPI_POINTER PTR_MPI_EXT_IMAGE_HEADER, 3588 MpiExtImageHeader_t, MPI_POINTER pMpiExtImageHeader_t; 3589 3590 /* defines for the ImageType field */ 3591 #define MPI_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 3592 #define MPI_EXT_IMAGE_TYPE_FW (0x01) 3593 #define MPI_EXT_IMAGE_TYPE_NVDATA (0x03) 3594 3595 #endif 3596 3597 /* 3598 * Copyright (c) 2000, 2001 by LSI Logic Corporation 3599 * 3600 * Redistribution and use in source and binary forms, with or without 3601 * modification, are permitted provided that the following conditions 3602 * are met: 3603 * 1. Redistributions of source code must retain the above copyright 3604 * notice immediately at the beginning of the file, without modification, 3605 * this list of conditions, and the following disclaimer. 3606 * 2. The name of the author may not be used to endorse or promote products 3607 * derived from this software without specific prior written permission. 3608 * 3609 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 3610 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 3611 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 3612 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 3613 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3614 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3615 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3616 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3617 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3618 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3619 * SUCH DAMAGE. 3620 * 3621 * 3622 * Name: MPI_LAN.H 3623 * Title: MPI LAN messages and structures 3624 * Creation Date: June 30, 2000 3625 * 3626 * MPI Version: 01.02.01 3627 * 3628 * Version History 3629 * --------------- 3630 * 3631 * Date Version Description 3632 * -------- -------- ------------------------------------------------------ 3633 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 3634 * 05-24-00 00.10.02 Added LANStatus field to _MSG_LAN_SEND_REPLY. 3635 * Added LANStatus field to _MSG_LAN_RECEIVE_POST_REPLY. 3636 * Moved ListCount field in _MSG_LAN_RECEIVE_POST_REPLY. 3637 * 06-06-00 01.00.01 Update version number for 1.0 release. 3638 * 06-12-00 01.00.02 Added MPI_ to BUCKETSTATUS_ definitions. 3639 * 06-22-00 01.00.03 Major changes to match new LAN definition in 1.0 spec. 3640 * 06-30-00 01.00.04 Added Context Reply definitions per revised proposal. 3641 * Changed transaction context usage to bucket/buffer. 3642 * 07-05-00 01.00.05 Removed LAN_RECEIVE_POST_BUCKET_CONTEXT_MASK definition 3643 * to lan private header file 3644 * 11-02-00 01.01.01 Original release for post 1.0 work 3645 * 02-20-01 01.01.02 Started using MPI_POINTER. 3646 * 03-27-01 01.01.03 Added structure offset comments. 3647 * 08-08-01 01.02.01 Original release for v1.2 work. 3648 * -------------------------------------------------------------------------- 3649 */ 3650 3651 #ifndef MPI_LAN_H 3652 #define MPI_LAN_H 3653 3654 3655 /****************************************************************************** 3656 * 3657 * L A N M e s s a g e s 3658 * 3659 *******************************************************************************/ 3660 3661 /* LANSend messages */ 3662 3663 typedef struct _MSG_LAN_SEND_REQUEST 3664 { 3665 U16 Reserved; /* 00h */ 3666 U8 ChainOffset; /* 02h */ 3667 U8 Function; /* 03h */ 3668 U16 Reserved2; /* 04h */ 3669 U8 PortNumber; /* 06h */ 3670 U8 MsgFlags; /* 07h */ 3671 U32 MsgContext; /* 08h */ 3672 SGE_MPI_UNION SG_List[1]; /* 0Ch */ 3673 } MSG_LAN_SEND_REQUEST, MPI_POINTER PTR_MSG_LAN_SEND_REQUEST, 3674 LANSendRequest_t, MPI_POINTER pLANSendRequest_t; 3675 3676 3677 typedef struct _MSG_LAN_SEND_REPLY 3678 { 3679 U16 Reserved; /* 00h */ 3680 U8 MsgLength; /* 02h */ 3681 U8 Function; /* 03h */ 3682 U8 Reserved2; /* 04h */ 3683 U8 NumberOfContexts; /* 05h */ 3684 U8 PortNumber; /* 06h */ 3685 U8 MsgFlags; /* 07h */ 3686 U32 MsgContext; /* 08h */ 3687 U16 Reserved3; /* 0Ch */ 3688 U16 IOCStatus; /* 0Eh */ 3689 U32 IOCLogInfo; /* 10h */ 3690 U32 BufferContext; /* 14h */ 3691 } MSG_LAN_SEND_REPLY, MPI_POINTER PTR_MSG_LAN_SEND_REPLY, 3692 LANSendReply_t, MPI_POINTER pLANSendReply_t; 3693 3694 3695 /* LANReceivePost */ 3696 3697 typedef struct _MSG_LAN_RECEIVE_POST_REQUEST 3698 { 3699 U16 Reserved; /* 00h */ 3700 U8 ChainOffset; /* 02h */ 3701 U8 Function; /* 03h */ 3702 U16 Reserved2; /* 04h */ 3703 U8 PortNumber; /* 06h */ 3704 U8 MsgFlags; /* 07h */ 3705 U32 MsgContext; /* 08h */ 3706 U32 BucketCount; /* 0Ch */ 3707 SGE_MPI_UNION SG_List[1]; /* 10h */ 3708 } MSG_LAN_RECEIVE_POST_REQUEST, MPI_POINTER PTR_MSG_LAN_RECEIVE_POST_REQUEST, 3709 LANReceivePostRequest_t, MPI_POINTER pLANReceivePostRequest_t; 3710 3711 3712 typedef struct _MSG_LAN_RECEIVE_POST_REPLY 3713 { 3714 U16 Reserved; /* 00h */ 3715 U8 MsgLength; /* 02h */ 3716 U8 Function; /* 03h */ 3717 U8 Reserved2; /* 04h */ 3718 U8 NumberOfContexts; /* 05h */ 3719 U8 PortNumber; /* 06h */ 3720 U8 MsgFlags; /* 07h */ 3721 U32 MsgContext; /* 08h */ 3722 U16 Reserved3; /* 0Ch */ 3723 U16 IOCStatus; /* 0Eh */ 3724 U32 IOCLogInfo; /* 10h */ 3725 U32 BucketsRemaining; /* 14h */ 3726 U32 PacketOffset; /* 18h */ 3727 U32 PacketLength; /* 1Ch */ 3728 U32 BucketContext[1]; /* 20h */ 3729 } MSG_LAN_RECEIVE_POST_REPLY, MPI_POINTER PTR_MSG_LAN_RECEIVE_POST_REPLY, 3730 LANReceivePostReply_t, MPI_POINTER pLANReceivePostReply_t; 3731 3732 3733 /* LANReset */ 3734 3735 typedef struct _MSG_LAN_RESET_REQUEST 3736 { 3737 U16 Reserved; /* 00h */ 3738 U8 ChainOffset; /* 02h */ 3739 U8 Function; /* 03h */ 3740 U16 Reserved2; /* 04h */ 3741 U8 PortNumber; /* 05h */ 3742 U8 MsgFlags; /* 07h */ 3743 U32 MsgContext; /* 08h */ 3744 } MSG_LAN_RESET_REQUEST, MPI_POINTER PTR_MSG_LAN_RESET_REQUEST, 3745 LANResetRequest_t, MPI_POINTER pLANResetRequest_t; 3746 3747 3748 typedef struct _MSG_LAN_RESET_REPLY 3749 { 3750 U16 Reserved; /* 00h */ 3751 U8 MsgLength; /* 02h */ 3752 U8 Function; /* 03h */ 3753 U16 Reserved2; /* 04h */ 3754 U8 PortNumber; /* 06h */ 3755 U8 MsgFlags; /* 07h */ 3756 U32 MsgContext; /* 08h */ 3757 U16 Reserved3; /* 0Ch */ 3758 U16 IOCStatus; /* 0Eh */ 3759 U32 IOCLogInfo; /* 10h */ 3760 } MSG_LAN_RESET_REPLY, MPI_POINTER PTR_MSG_LAN_RESET_REPLY, 3761 LANResetReply_t, MPI_POINTER pLANResetReply_t; 3762 3763 3764 /****************************************************************************/ 3765 /* LAN Context Reply defines and macros */ 3766 /****************************************************************************/ 3767 3768 #define LAN_REPLY_PACKET_LENGTH_MASK (0x0000FFFF) 3769 #define LAN_REPLY_PACKET_LENGTH_SHIFT (0) 3770 #define LAN_REPLY_BUCKET_CONTEXT_MASK (0x07FF0000) 3771 #define LAN_REPLY_BUCKET_CONTEXT_SHIFT (16) 3772 #define LAN_REPLY_BUFFER_CONTEXT_MASK (0x07FFFFFF) 3773 #define LAN_REPLY_BUFFER_CONTEXT_SHIFT (0) 3774 #define LAN_REPLY_FORM_MASK (0x18000000) 3775 #define LAN_REPLY_FORM_RECEIVE_SINGLE (0x00) 3776 #define LAN_REPLY_FORM_RECEIVE_MULTIPLE (0x01) 3777 #define LAN_REPLY_FORM_SEND_SINGLE (0x02) 3778 #define LAN_REPLY_FORM_MESSAGE_CONTEXT (0x03) 3779 #define LAN_REPLY_FORM_SHIFT (27) 3780 3781 #define GET_LAN_PACKET_LENGTH(x) (((x) & LAN_REPLY_PACKET_LENGTH_MASK) \ 3782 >> LAN_REPLY_PACKET_LENGTH_SHIFT) 3783 3784 #define SET_LAN_PACKET_LENGTH(x, lth) \ 3785 ((x) = ((x) & ~LAN_REPLY_PACKET_LENGTH_MASK) | \ 3786 (((lth) << LAN_REPLY_PACKET_LENGTH_SHIFT) & \ 3787 LAN_REPLY_PACKET_LENGTH_MASK)) 3788 3789 #define GET_LAN_BUCKET_CONTEXT(x) (((x) & LAN_REPLY_BUCKET_CONTEXT_MASK) \ 3790 >> LAN_REPLY_BUCKET_CONTEXT_SHIFT) 3791 3792 #define SET_LAN_BUCKET_CONTEXT(x, ctx) \ 3793 ((x) = ((x) & ~LAN_REPLY_BUCKET_CONTEXT_MASK) | \ 3794 (((ctx) << LAN_REPLY_BUCKET_CONTEXT_SHIFT) & \ 3795 LAN_REPLY_BUCKET_CONTEXT_MASK)) 3796 3797 #define GET_LAN_BUFFER_CONTEXT(x) (((x) & LAN_REPLY_BUFFER_CONTEXT_MASK) \ 3798 >> LAN_REPLY_BUFFER_CONTEXT_SHIFT) 3799 3800 #define SET_LAN_BUFFER_CONTEXT(x, ctx) \ 3801 ((x) = ((x) & ~LAN_REPLY_BUFFER_CONTEXT_MASK) | \ 3802 (((ctx) << LAN_REPLY_BUFFER_CONTEXT_SHIFT) & \ 3803 LAN_REPLY_BUFFER_CONTEXT_MASK)) 3804 3805 #define GET_LAN_FORM(x) (((x) & LAN_REPLY_FORM_MASK) \ 3806 >> LAN_REPLY_FORM_SHIFT) 3807 3808 #define SET_LAN_FORM(x, frm) \ 3809 ((x) = ((x) & ~LAN_REPLY_FORM_MASK) | \ 3810 (((frm) << LAN_REPLY_FORM_SHIFT) & \ 3811 LAN_REPLY_FORM_MASK)) 3812 3813 3814 /****************************************************************************/ 3815 /* LAN Current Device State defines */ 3816 /****************************************************************************/ 3817 3818 #define MPI_LAN_DEVICE_STATE_RESET (0x00) 3819 #define MPI_LAN_DEVICE_STATE_OPERATIONAL (0x01) 3820 3821 3822 /****************************************************************************/ 3823 /* LAN Loopback defines */ 3824 /****************************************************************************/ 3825 3826 #define MPI_LAN_TX_MODES_ENABLE_LOOPBACK_SUPPRESSION (0x01) 3827 3828 #endif 3829 3830 3831 /* 3832 * Copyright (c) 2000, 2001 by LSI Logic Corporation 3833 * 3834 * Redistribution and use in source and binary forms, with or without 3835 * modification, are permitted provided that the following conditions 3836 * are met: 3837 * 1. Redistributions of source code must retain the above copyright 3838 * notice immediately at the beginning of the file, without modification, 3839 * this list of conditions, and the following disclaimer. 3840 * 2. The name of the author may not be used to endorse or promote products 3841 * derived from this software without specific prior written permission. 3842 * 3843 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 3844 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 3845 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 3846 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 3847 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3848 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3849 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3850 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3851 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3852 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3853 * SUCH DAMAGE. 3854 * 3855 * 3856 * Name: MPI_TARG.H 3857 * Title: MPI Target mode messages and structures 3858 * Creation Date: June 22, 2000 3859 * 3860 * MPI Version: 01.02.04 3861 * 3862 * Version History 3863 * --------------- 3864 * 3865 * Date Version Description 3866 * -------- -------- ------------------------------------------------------ 3867 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 3868 * 06-06-00 01.00.01 Update version number for 1.0 release. 3869 * 06-22-00 01.00.02 Added _MSG_TARGET_CMD_BUFFER_POST_REPLY structure. 3870 * Corrected DECSRIPTOR typo to DESCRIPTOR. 3871 * 11-02-00 01.01.01 Original release for post 1.0 work 3872 * Modified target mode to use IoIndex instead of 3873 * HostIndex and IocIndex. Added Alias. 3874 * 01-09-01 01.01.02 Added defines for TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER 3875 * and TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER. 3876 * 02-20-01 01.01.03 Started using MPI_POINTER. 3877 * Added structures for MPI_TARGET_SCSI_SPI_CMD_BUFFER and 3878 * MPI_TARGET_FCP_CMD_BUFFER. 3879 * 03-27-01 01.01.04 Added structure offset comments. 3880 * 08-08-01 01.02.01 Original release for v1.2 work. 3881 * 09-28-01 01.02.02 Added structure for MPI_TARGET_SCSI_SPI_STATUS_IU. 3882 * Added PriorityReason field to some replies and 3883 * defined more PriorityReason codes. 3884 * Added some defines for to support previous version 3885 * of MPI. 3886 * 10-04-01 01.02.03 Added PriorityReason to MSG_TARGET_ERROR_REPLY. 3887 * 11-01-01 01.02.04 Added define for TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY. 3888 * -------------------------------------------------------------------------- 3889 */ 3890 3891 #ifndef MPI_TARG_H 3892 #define MPI_TARG_H 3893 3894 3895 /****************************************************************************** 3896 * 3897 * S C S I T a r g e t M e s s a g e s 3898 * 3899 *******************************************************************************/ 3900 3901 typedef struct _CMD_BUFFER_DESCRIPTOR 3902 { 3903 U16 IoIndex; /* 00h */ 3904 U16 Reserved; /* 02h */ 3905 union /* 04h */ 3906 { 3907 U32 PhysicalAddress32; 3908 U64 PhysicalAddress64; 3909 } _u; 3910 } CMD_BUFFER_DESCRIPTOR, MPI_POINTER PTR_CMD_BUFFER_DESCRIPTOR, 3911 CmdBufferDescriptor_t, MPI_POINTER pCmdBufferDescriptor_t; 3912 3913 3914 /****************************************************************************/ 3915 /* Target Command Buffer Post Request */ 3916 /****************************************************************************/ 3917 3918 typedef struct _MSG_TARGET_CMD_BUFFER_POST_REQUEST 3919 { 3920 U8 BufferPostFlags; /* 00h */ 3921 U8 BufferCount; /* 01h */ 3922 U8 ChainOffset; /* 02h */ 3923 U8 Function; /* 03h */ 3924 U8 BufferLength; /* 04h */ 3925 U8 Reserved; /* 05h */ 3926 U8 Reserved1; /* 06h */ 3927 U8 MsgFlags; /* 07h */ 3928 U32 MsgContext; /* 08h */ 3929 CMD_BUFFER_DESCRIPTOR Buffer[1]; /* 0Ch */ 3930 } MSG_TARGET_CMD_BUFFER_POST_REQUEST, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REQUEST, 3931 TargetCmdBufferPostRequest_t, MPI_POINTER pTargetCmdBufferPostRequest_t; 3932 3933 #define CMD_BUFFER_POST_FLAGS_PORT_MASK (0x01) 3934 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_MASK (0x80) 3935 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_32 (0) 3936 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_64 (1) 3937 #define CMD_BUFFER_POST_FLAGS_64_BIT_ADDR (0x80) 3938 3939 #define CMD_BUFFER_POST_IO_INDEX_MASK (0x00003FFF) 3940 #define CMD_BUFFER_POST_IO_INDEX_MASK_0100 (0x000003FF) /* obsolete */ 3941 3942 3943 typedef struct _MSG_TARGET_CMD_BUFFER_POST_REPLY 3944 { 3945 U8 BufferPostFlags; /* 00h */ 3946 U8 BufferCount; /* 01h */ 3947 U8 MsgLength; /* 02h */ 3948 U8 Function; /* 03h */ 3949 U8 BufferLength; /* 04h */ 3950 U8 Reserved; /* 05h */ 3951 U8 Reserved1; /* 06h */ 3952 U8 MsgFlags; /* 07h */ 3953 U32 MsgContext; /* 08h */ 3954 U16 Reserved2; /* 0Ch */ 3955 U16 IOCStatus; /* 0Eh */ 3956 U32 IOCLogInfo; /* 10h */ 3957 } MSG_TARGET_CMD_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REPLY, 3958 TargetCmdBufferPostReply_t, MPI_POINTER pTargetCmdBufferPostReply_t; 3959 3960 /* the following structure is obsolete as of MPI v1.2 */ 3961 typedef struct _MSG_PRIORITY_CMD_RECEIVED_REPLY 3962 { 3963 U16 Reserved; /* 00h */ 3964 U8 MsgLength; /* 02h */ 3965 U8 Function; /* 03h */ 3966 U16 Reserved1; /* 04h */ 3967 U8 Reserved2; /* 06h */ 3968 U8 MsgFlags; /* 07h */ 3969 U32 MsgContext; /* 08h */ 3970 U8 PriorityReason; /* 0Ch */ 3971 U8 Reserved3; /* 0Dh */ 3972 U16 IOCStatus; /* 0Eh */ 3973 U32 IOCLogInfo; /* 10h */ 3974 U32 ReplyWord; /* 14h */ 3975 } MSG_PRIORITY_CMD_RECEIVED_REPLY, MPI_POINTER PTR_MSG_PRIORITY_CMD_RECEIVED_REPLY, 3976 PriorityCommandReceivedReply_t, MPI_POINTER pPriorityCommandReceivedReply_t; 3977 3978 #define PRIORITY_REASON_NO_DISCONNECT (0x00) 3979 #define PRIORITY_REASON_SCSI_TASK_MANAGEMENT (0x01) 3980 #define PRIORITY_REASON_CMD_PARITY_ERR (0x02) 3981 #define PRIORITY_REASON_MSG_OUT_PARITY_ERR (0x03) 3982 #define PRIORITY_REASON_LQ_CRC_ERR (0x04) 3983 #define PRIORITY_REASON_CMD_CRC_ERR (0x05) 3984 #define PRIORITY_REASON_PROTOCOL_ERR (0x06) 3985 #define PRIORITY_REASON_DATA_OUT_PARITY_ERR (0x07) 3986 #define PRIORITY_REASON_DATA_OUT_CRC_ERR (0x08) 3987 #define PRIORITY_REASON_UNKNOWN (0xFF) 3988 3989 3990 typedef struct _MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY 3991 { 3992 U16 Reserved; /* 00h */ 3993 U8 MsgLength; /* 02h */ 3994 U8 Function; /* 03h */ 3995 U16 Reserved1; /* 04h */ 3996 U8 Reserved2; /* 06h */ 3997 U8 MsgFlags; /* 07h */ 3998 U32 MsgContext; /* 08h */ 3999 U8 PriorityReason; /* 0Ch */ 4000 U8 Reserved3; /* 0Dh */ 4001 U16 IOCStatus; /* 0Eh */ 4002 U32 IOCLogInfo; /* 10h */ 4003 U32 ReplyWord; /* 14h */ 4004 } MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY, 4005 MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY, 4006 TargetCmdBufferPostErrorReply_t, MPI_POINTER pTargetCmdBufferPostErrorReply_t; 4007 4008 4009 typedef struct _MPI_TARGET_FCP_CMD_BUFFER 4010 { 4011 U8 FcpLun[8]; /* 00h */ 4012 U8 FcpCntl[4]; /* 08h */ 4013 U8 FcpCdb[16]; /* 0Ch */ 4014 U32 FcpDl; /* 1Ch */ 4015 } MPI_TARGET_FCP_CMD_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_CMD_BUFFER, 4016 MpiTargetFcpCmdBuffer, MPI_POINTER pMpiTargetFcpCmdBuffer; 4017 4018 4019 typedef struct _MPI_TARGET_SCSI_SPI_CMD_BUFFER 4020 { 4021 /* SPI L_Q information unit */ 4022 U8 L_QType; /* 00h */ 4023 U8 Reserved; /* 01h */ 4024 U16 Tag; /* 02h */ 4025 U8 LogicalUnitNumber[8]; /* 04h */ 4026 U32 DataLength; /* 0Ch */ 4027 /* SPI command information unit */ 4028 U8 ReservedFirstByteOfCommandIU; /* 10h */ 4029 U8 TaskAttribute; /* 11h */ 4030 U8 TaskManagementFlags; /* 12h */ 4031 U8 AdditionalCDBLength; /* 13h */ 4032 U8 CDB[16]; /* 14h */ 4033 } MPI_TARGET_SCSI_SPI_CMD_BUFFER, 4034 MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_CMD_BUFFER, 4035 MpiTargetScsiSpiCmdBuffer, MPI_POINTER pMpiTargetScsiSpiCmdBuffer; 4036 4037 4038 /****************************************************************************/ 4039 /* Target Assist Request */ 4040 /****************************************************************************/ 4041 4042 typedef struct _MSG_TARGET_ASSIST_REQUEST 4043 { 4044 U8 StatusCode; /* 00h */ 4045 U8 TargetAssistFlags; /* 01h */ 4046 U8 ChainOffset; /* 02h */ 4047 U8 Function; /* 03h */ 4048 U16 QueueTag; /* 04h */ 4049 U8 Reserved; /* 06h */ 4050 U8 MsgFlags; /* 07h */ 4051 U32 MsgContext; /* 08h */ 4052 U32 ReplyWord; /* 0Ch */ 4053 U8 LUN[8]; /* 10h */ 4054 U32 RelativeOffset; /* 18h */ 4055 U32 DataLength; /* 1Ch */ 4056 SGE_IO_UNION SGL[1]; /* 20h */ 4057 } MSG_TARGET_ASSIST_REQUEST, MPI_POINTER PTR_MSG_TARGET_ASSIST_REQUEST, 4058 TargetAssistRequest_t, MPI_POINTER pTargetAssistRequest_t; 4059 4060 #define TARGET_ASSIST_FLAGS_DATA_DIRECTION (0x01) 4061 #define TARGET_ASSIST_FLAGS_AUTO_STATUS (0x02) 4062 #define TARGET_ASSIST_FLAGS_HIGH_PRIORITY (0x04) 4063 #define TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x80) 4064 4065 4066 typedef struct _MSG_TARGET_ERROR_REPLY 4067 { 4068 U16 Reserved; /* 00h */ 4069 U8 MsgLength; /* 02h */ 4070 U8 Function; /* 03h */ 4071 U16 Reserved1; /* 04h */ 4072 U8 Reserved2; /* 06h */ 4073 U8 MsgFlags; /* 07h */ 4074 U32 MsgContext; /* 08h */ 4075 U8 PriorityReason; /* 0Ch */ 4076 U8 Reserved3; /* 0Dh */ 4077 U16 IOCStatus; /* 0Eh */ 4078 U32 IOCLogInfo; /* 10h */ 4079 U32 ReplyWord; /* 14h */ 4080 U32 TransferCount; /* 18h */ 4081 } MSG_TARGET_ERROR_REPLY, MPI_POINTER PTR_MSG_TARGET_ERROR_REPLY, 4082 TargetErrorReply_t, MPI_POINTER pTargetErrorReply_t; 4083 4084 4085 /****************************************************************************/ 4086 /* Target Status Send Request */ 4087 /****************************************************************************/ 4088 4089 typedef struct _MSG_TARGET_STATUS_SEND_REQUEST 4090 { 4091 U8 StatusCode; /* 00h */ 4092 U8 StatusFlags; /* 01h */ 4093 U8 ChainOffset; /* 02h */ 4094 U8 Function; /* 03h */ 4095 U16 QueueTag; /* 04h */ 4096 U8 Reserved; /* 06h */ 4097 U8 MsgFlags; /* 07h */ 4098 U32 MsgContext; /* 08h */ 4099 U32 ReplyWord; /* 0Ch */ 4100 U8 LUN[8]; /* 10h */ 4101 SGE_SIMPLE_UNION StatusDataSGE; /* 18h */ 4102 } MSG_TARGET_STATUS_SEND_REQUEST, MPI_POINTER PTR_MSG_TARGET_STATUS_SEND_REQUEST, 4103 TargetStatusSendRequest_t, MPI_POINTER pTargetStatusSendRequest_t; 4104 4105 #define TARGET_STATUS_SEND_FLAGS_AUTO_GOOD_STATUS (0x01) 4106 #define TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY (0x04) 4107 #define TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER (0x80) 4108 4109 typedef struct _MPI_TARGET_FCP_RSP_BUFFER 4110 { 4111 U8 Reserved0[8]; /* 00h */ 4112 U8 FcpStatus; /* 08h */ 4113 U8 FcpFlags; /* 09h */ 4114 U8 Reserved1[2]; /* 0Ah */ 4115 U32 FcpResid; /* 0Ch */ 4116 U32 FcpSenseLength; /* 10h */ 4117 U32 FcpResponseLength; /* 14h */ 4118 U8 FcpResponseData[8]; /* 18h */ 4119 U8 FcpSenseData[32]; /* Pad to 64 bytes */ /* 20h */ 4120 } MPI_TARGET_FCP_RSP_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_RSP_BUFFER, 4121 MpiTargetFcpRspBuffer, MPI_POINTER pMpiTargetFcpRspBuffer; 4122 4123 typedef struct _MPI_TARGET_SCSI_SPI_STATUS_IU 4124 { 4125 U8 Reserved0; /* 00h */ 4126 U8 Reserved1; /* 01h */ 4127 U8 Valid; /* 02h */ 4128 U8 Status; /* 03h */ 4129 U32 SenseDataListLength; /* 04h */ 4130 U32 PktFailuresListLength; /* 08h */ 4131 U8 SenseData[52]; /* Pad the IU to 64 bytes */ /* 0Ch */ 4132 } MPI_TARGET_SCSI_SPI_STATUS_IU, MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_STATUS_IU, 4133 TargetScsiSpiStatusIU_t, MPI_POINTER pTargetScsiSpiStatusIU_t; 4134 4135 /****************************************************************************/ 4136 /* Target Mode Abort Request */ 4137 /****************************************************************************/ 4138 4139 typedef struct _MSG_TARGET_MODE_ABORT_REQUEST 4140 { 4141 U8 AbortType; /* 00h */ 4142 U8 Reserved; /* 01h */ 4143 U8 ChainOffset; /* 02h */ 4144 U8 Function; /* 03h */ 4145 U16 Reserved1; /* 04h */ 4146 U8 Reserved2; /* 06h */ 4147 U8 MsgFlags; /* 07h */ 4148 U32 MsgContext; /* 08h */ 4149 U32 ReplyWord; /* 0Ch */ 4150 U32 MsgContextToAbort; /* 10h */ 4151 } MSG_TARGET_MODE_ABORT, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT, 4152 TargetModeAbort_t, MPI_POINTER pTargetModeAbort_t; 4153 4154 #define TARGET_MODE_ABORT_TYPE_ALL_CMD_BUFFERS (0x00) 4155 #define TARGET_MODE_ABORT_TYPE_ALL_IO (0x01) 4156 #define TARGET_MODE_ABORT_TYPE_EXACT_IO (0x02) 4157 #define TARGET_MODE_ABORT_TYPE_EXACT_IO_REQUEST (0x03) 4158 4159 /* Target Mode Abort Reply */ 4160 4161 typedef struct _MSG_TARGET_MODE_ABORT_REPLY 4162 { 4163 U16 Reserved; /* 00h */ 4164 U8 MsgLength; /* 02h */ 4165 U8 Function; /* 03h */ 4166 U16 Reserved1; /* 04h */ 4167 U8 Reserved2; /* 06h */ 4168 U8 MsgFlags; /* 07h */ 4169 U32 MsgContext; /* 08h */ 4170 U16 Reserved3; /* 0Ch */ 4171 U16 IOCStatus; /* 0Eh */ 4172 U32 IOCLogInfo; /* 10h */ 4173 U32 AbortCount; /* 14h */ 4174 } MSG_TARGET_MODE_ABORT_REPLY, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT_REPLY, 4175 TargetModeAbortReply_t, MPI_POINTER pTargetModeAbortReply_t; 4176 4177 4178 /****************************************************************************/ 4179 /* Target Mode Context Reply */ 4180 /****************************************************************************/ 4181 4182 #define TARGET_MODE_REPLY_IO_INDEX_MASK (0x00003FFF) 4183 #define TARGET_MODE_REPLY_IO_INDEX_SHIFT (0) 4184 #define TARGET_MODE_REPLY_INITIATOR_INDEX_MASK (0x03FFC000) 4185 #define TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT (14) 4186 #define TARGET_MODE_REPLY_ALIAS_MASK (0x0C000000) 4187 #define TARGET_MODE_REPLY_ALIAS_SHIFT (26) 4188 #define TARGET_MODE_REPLY_PORT_MASK (0x10000000) 4189 #define TARGET_MODE_REPLY_PORT_SHIFT (28) 4190 4191 4192 #define GET_IO_INDEX(x) (((x) & TARGET_MODE_REPLY_IO_INDEX_MASK) \ 4193 >> TARGET_MODE_REPLY_IO_INDEX_SHIFT) 4194 4195 #define SET_IO_INDEX(t, i) \ 4196 ((t) = ((t) & ~TARGET_MODE_REPLY_IO_INDEX_MASK) | \ 4197 (((i) << TARGET_MODE_REPLY_IO_INDEX_SHIFT) & \ 4198 TARGET_MODE_REPLY_IO_INDEX_MASK)) 4199 4200 #define GET_INITIATOR_INDEX(x) (((x) & TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) \ 4201 >> TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) 4202 4203 #define SET_INITIATOR_INDEX(t, ii) \ 4204 ((t) = ((t) & ~TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) | \ 4205 (((ii) << TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) & \ 4206 TARGET_MODE_REPLY_INITIATOR_INDEX_MASK)) 4207 4208 #define GET_ALIAS(x) (((x) & TARGET_MODE_REPLY_ALIAS_MASK) \ 4209 >> TARGET_MODE_REPLY_ALIAS_SHIFT) 4210 4211 #define SET_ALIAS(t, a) ((t) = ((t) & ~TARGET_MODE_REPLY_ALIAS_MASK) | \ 4212 (((a) << TARGET_MODE_REPLY_ALIAS_SHIFT) & \ 4213 TARGET_MODE_REPLY_ALIAS_MASK)) 4214 4215 #define GET_PORT(x) (((x) & TARGET_MODE_REPLY_PORT_MASK) \ 4216 >> TARGET_MODE_REPLY_PORT_SHIFT) 4217 4218 #define SET_PORT(t, p) ((t) = ((t) & ~TARGET_MODE_REPLY_PORT_MASK) | \ 4219 (((p) << TARGET_MODE_REPLY_PORT_SHIFT) & \ 4220 TARGET_MODE_REPLY_PORT_MASK)) 4221 4222 /* the following obsolete values are for MPI v1.0 support */ 4223 #define TARGET_MODE_REPLY_0100_MASK_HOST_INDEX (0x000003FF) 4224 #define TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX (0) 4225 #define TARGET_MODE_REPLY_0100_MASK_IOC_INDEX (0x001FF800) 4226 #define TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX (11) 4227 #define TARGET_MODE_REPLY_0100_PORT_MASK (0x00400000) 4228 #define TARGET_MODE_REPLY_0100_PORT_SHIFT (22) 4229 #define TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX (0x1F800000) 4230 #define TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX (23) 4231 4232 #define GET_HOST_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) \ 4233 >> TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) 4234 4235 #define SET_HOST_INDEX_0100(t, hi) \ 4236 ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) | \ 4237 (((hi) << TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) & \ 4238 TARGET_MODE_REPLY_0100_MASK_HOST_INDEX)) 4239 4240 #define GET_IOC_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) \ 4241 >> TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) 4242 4243 #define SET_IOC_INDEX_0100(t, ii) \ 4244 ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) | \ 4245 (((ii) << TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) & \ 4246 TARGET_MODE_REPLY_0100_MASK_IOC_INDEX)) 4247 4248 #define GET_INITIATOR_INDEX_0100(x) \ 4249 (((x) & TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) \ 4250 >> TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) 4251 4252 #define SET_INITIATOR_INDEX_0100(t, ii) \ 4253 ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) | \ 4254 (((ii) << TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) & \ 4255 TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX)) 4256 4257 4258 #endif 4259 4260