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Searched refs:BIU_ICR_ENABLE_RISC_INT (Results 1 – 1 of 1) sorted by relevance

/mirbsd/src/sys/dev/ic/
Dispreg.h217 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ macro
231 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \
235 (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\