1 /* $OpenBSD: maestro_reg.h,v 1.1 2001/01/11 23:36:38 espie Exp $ */ 2 /*- 3 * Copyright (c) 1999-2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $Id: maestro_reg.h,v 1.1 2001/01/11 23:36:38 espie Exp $ 28 * $FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro_reg.h,v 1.1 2000/09/06 20:10:54 cg Exp $ 29 */ 30 31 #ifndef MAESTRO_REG_H_INCLUDED 32 #define MAESTRO_REG_H_INCLUDED 33 34 /* ----------------------------- 35 * PCI config registers 36 */ 37 38 /* Legacy emulation */ 39 #define CONF_LEGACY 0x40 40 41 #define LEGACY_DISABLED 0x8000 42 43 /* Chip configurations */ 44 #define CONF_MAESTRO 0x50 45 #define MAESTRO_CHIBUS 0x00100000 46 #define MAESTRO_POSTEDWRITE 0x00000080 47 #define MAESTRO_DMA_PCITIMING 0x00000040 48 #define MAESTRO_SWAP_LR 0x00000010 49 50 /* ACPI configurations */ 51 #define CONF_ACPI_STOPCLOCK 0x54 52 #define ACPI_PART_2ndC_CLOCK 15 53 #define ACPI_PART_CODEC_CLOCK 14 54 #define ACPI_PART_978 13 /* Docking station or something */ 55 #define ACPI_PART_SPDIF 12 56 #define ACPI_PART_GLUE 11 /* What? */ 57 #define ACPI_PART_DAA 10 58 #define ACPI_PART_PCI_IF 9 59 #define ACPI_PART_HW_VOL 8 60 #define ACPI_PART_GPIO 7 61 #define ACPI_PART_ASSP 6 62 #define ACPI_PART_SB 5 63 #define ACPI_PART_FM 4 64 #define ACPI_PART_RINGBUS 3 65 #define ACPI_PART_MIDI 2 66 #define ACPI_PART_GAME_PORT 1 67 #define ACPI_PART_WP 0 68 69 /* Power management */ 70 #define CONF_PM_PTR 0x34 /* BYTE R */ 71 #define PM_CID 0 /* BYTE R */ 72 #define PPMI_CID 1 73 #define PM_CTRL 4 /* BYTE RW */ 74 #define PPMI_D0 0 /* Full power */ 75 #define PPMI_D1 1 /* Medium power */ 76 #define PPMI_D2 2 /* Low power */ 77 #define PPMI_D3 3 /* Turned off */ 78 79 80 /* ----------------------------- 81 * I/O ports 82 */ 83 84 /* Direct Sound Processor (aka Wave Processor) */ 85 #define PORT_DSP_DATA 0x00 /* WORD RW */ 86 #define PORT_DSP_INDEX 0x02 /* WORD RW */ 87 #define PORT_INT_STAT 0x04 /* WORD RW */ 88 #define PORT_SAMPLE_CNT 0x06 /* WORD RO */ 89 90 /* WaveCache */ 91 #define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */ 92 #define PORT_WAVCACHE_DATA 0x12 /* WORD RW */ 93 #define WAVCACHE_PCMBAR 0x1fc 94 #define WAVCACHE_WTBAR 0x1f0 95 #define WAVCACHE_BASEADDR_SHIFT 12 96 97 #define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8 98 #define WAVCACHE_CHCTL_U8 0x0004 99 #define WAVCACHE_CHCTL_STEREO 0x0002 100 #define WAVCACHE_CHCTL_DECREMENTAL 0x0001 101 102 #define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */ 103 #define WAVCACHE_EXTRA_CH_ENABLED 0x0200 104 #define WAVCACHE_ENABLED 0x0100 105 #define WAVCACHE_CH_60_ENABLED 0x0080 106 #define WAVCACHE_WTSIZE_MASK 0x0060 107 #define WAVCACHE_WTSIZE_1MB 0x0000 108 #define WAVCACHE_WTSIZE_2MB 0x0020 109 #define WAVCACHE_WTSIZE_4MB 0x0040 110 #define WAVCACHE_WTSIZE_8MB 0x0060 111 #define WAVCACHE_SGC_MASK 0x000c 112 #define WAVCACHE_SGC_DISABLED 0x0000 113 #define WAVCACHE_SGC_40_47 0x0004 114 #define WAVCACHE_SGC_32_47 0x0008 115 #define WAVCACHE_TESTMODE 0x0001 116 117 /* Host Interruption */ 118 #define PORT_HOSTINT_CTRL 0x18 /* WORD RW */ 119 #define HOSTINT_CTRL_SOFT_RESET 0x8000 120 #define HOSTINT_CTRL_DSOUND_RESET 0x4000 121 #define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400 122 #define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100 123 #define HOSTINT_CTRL_HWVOL_ENABLED 0x0040 124 #define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010 125 #define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008 126 #define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004 127 #define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002 128 #define HOSTINT_CTRL_SB_INT_ENABLED 0x0001 129 130 #define PORT_HOSTINT_STAT 0x1a /* BYTE RW */ 131 #define HOSTINT_STAT_HWVOL 0x40 132 #define HOSTINT_STAT_ASSP 0x10 133 #define HOSTINT_STAT_ISDN 0x08 134 #define HOSTINT_STAT_DSOUND 0x04 135 #define HOSTINT_STAT_MPU401 0x02 136 #define HOSTINT_STAT_SB 0x01 137 138 /* Hardware volume */ 139 #define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */ 140 #define PORT_HWVOL_VOICE 0x1d /* BYTE RW */ 141 #define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */ 142 #define PORT_HWVOL_MASTER 0x1f /* BYTE RW */ 143 144 /* CODEC */ 145 #define PORT_CODEC_CMD 0x30 /* BYTE W */ 146 #define CODEC_CMD_READ 0x80 147 #define CODEC_CMD_WRITE 0x00 148 #define CODEC_CMD_ADDR_MASK 0x7f 149 150 #define PORT_CODEC_STAT 0x30 /* BYTE R */ 151 #define CODEC_STAT_MASK 0x01 152 #define CODEC_STAT_RW_DONE 0x00 153 #define CODEC_STAT_PROGLESS 0x01 154 155 #define PORT_CODEC_REG 0x32 /* WORD RW */ 156 157 /* Ring bus control */ 158 #define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */ 159 #define RINGBUS_CTRL_I2S_ENABLED 0x80000000 160 #define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000 161 #define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000 162 #define RINGBUS_CTRL_AC97_SWRESET 0x08000000 163 #define RINGBUS_CTRL_IODMA_PLAYBACK_ENABLED 0x04000000 164 #define RINGBUS_CTRL_IODMA_RECORD_ENABLED 0x02000000 165 166 #define RINGBUS_SRC_MIC 20 167 #define RINGBUS_SRC_I2S 16 168 #define RINGBUS_SRC_ADC 12 169 #define RINGBUS_SRC_MODEM 8 170 #define RINGBUS_SRC_DSOUND 4 171 #define RINGBUS_SRC_ASSP 0 172 173 #define RINGBUS_DEST_MONORAL 000 174 #define RINGBUS_DEST_STEREO 010 175 #define RINGBUS_DEST_NONE 0 176 #define RINGBUS_DEST_DAC 1 177 #define RINGBUS_DEST_MODEM_IN 2 178 #define RINGBUS_DEST_RESERVED3 3 179 #define RINGBUS_DEST_DSOUND_IN 4 180 #define RINGBUS_DEST_ASSP_IN 5 181 182 /* General Purpose I/O */ 183 #define PORT_GPIO_DATA 0x60 /* WORD RW */ 184 #define PORT_GPIO_MASK 0x64 /* WORD RW */ 185 #define PORT_GPIO_DIR 0x68 /* WORD RW */ 186 187 /* Application Specific Signal Processor */ 188 #define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */ 189 #define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */ 190 #define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */ 191 #define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */ 192 #define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */ 193 #define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */ 194 #define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */ 195 #define PORT_ASSP_INT_STAT 0xac /* BYTE RW */ 196 197 198 /* ----------------------------- 199 * Wave Processor Indexed Data Registers. 200 */ 201 202 #define WPREG_DATA_PORT 0 203 #define WPREG_CRAM_PTR 1 204 #define WPREG_CRAM_DATA 2 205 #define WPREG_WAVE_DATA 3 206 #define WPREG_WAVE_PTR_LOW 4 207 #define WPREG_WAVE_PTR_HIGH 5 208 209 #define WPREG_TIMER_FREQ 6 210 #define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */ 211 #define WP_TIMER_FREQ_PRESCALE_SHIFT 5 212 #define WP_TIMER_FREQ_DIVIDE_MASK 0x001f 213 #define WP_TIMER_FREQ_DIVIDE_SHIFT 0 214 215 #define WPREG_WAVE_ROMRAM 7 216 #define WP_WAVE_VIRTUAL_ENABLED 0x0400 217 #define WP_WAVE_8BITRAM_ENABLED 0x0200 218 #define WP_WAVE_DRAM_ENABLED 0x0100 219 #define WP_WAVE_RAMSPLIT_MASK 0x00ff 220 #define WP_WAVE_RAMSPLIT_SHIFT 0 221 222 #define WPREG_BASE 12 223 #define WP_PARAOUT_BASE_MASK 0xf000 224 #define WP_PARAOUT_BASE_SHIFT 12 225 #define WP_PARAIN_BASE_MASK 0x0f00 226 #define WP_PARAIN_BASE_SHIFT 8 227 #define WP_SERIAL0_BASE_MASK 0x00f0 228 #define WP_SERIAL0_BASE_SHIFT 4 229 #define WP_SERIAL1_BASE_MASK 0x000f 230 #define WP_SERIAL1_BASE_SHIFT 0 231 232 #define WPREG_TIMER_ENABLE 17 233 #define WPREG_TIMER_START 23 234 235 236 /* ----------------------------- 237 * Audio Processing Unit. 238 */ 239 #define APUREG_APUTYPE 0 240 #define APU_DMA_ENABLED 0x4000 241 #define APU_INT_ON_LOOP 0x2000 242 #define APU_ENDCURVE 0x1000 243 #define APU_APUTYPE_MASK 0x00f0 244 #define APU_FILTERTYPE_MASK 0x000c 245 #define APU_FILTERQ_MASK 0x0003 246 247 /* APU types */ 248 #define APU_APUTYPE_SHIFT 4 249 250 #define APUTYPE_INACTIVE 0 251 #define APUTYPE_16BITLINEAR 1 252 #define APUTYPE_16BITSTEREO 2 253 #define APUTYPE_8BITLINEAR 3 254 #define APUTYPE_8BITSTEREO 4 255 #define APUTYPE_8BITDIFF 5 256 #define APUTYPE_DIGITALDELAY 6 257 #define APUTYPE_DUALTAP_READER 7 258 #define APUTYPE_CORRELATOR 8 259 #define APUTYPE_INPUTMIXER 9 260 #define APUTYPE_WAVETABLE 10 261 #define APUTYPE_RATECONV 11 262 #define APUTYPE_16BITPINGPONG 12 263 /* APU type 13 through 15 are reserved. */ 264 265 /* Filter types */ 266 #define APU_FILTERTYPE_SHIFT 2 267 268 #define FILTERTYPE_2POLE_LOPASS 0 269 #define FILTERTYPE_2POLE_BANDPASS 1 270 #define FILTERTYPE_2POLE_HIPASS 2 271 #define FILTERTYPE_1POLE_LOPASS 3 272 #define FILTERTYPE_1POLE_HIPASS 4 273 #define FILTERTYPE_PASSTHROUGH 5 274 275 /* Filter Q */ 276 #define APU_FILTERQ_SHIFT 0 277 278 #define FILTERQ_LESSQ 0 279 #define FILTERQ_MOREQ 3 280 281 /* APU register 2 */ 282 #define APUREG_FREQ_LOBYTE 2 283 #define APU_FREQ_LOBYTE_MASK 0xff00 284 #define APU_plus6dB 0x0010 285 286 /* APU register 3 */ 287 #define APUREG_FREQ_HIWORD 3 288 #define APU_FREQ_HIWORD_MASK 0x0fff 289 290 /* Frequency */ 291 #define APU_FREQ_LOBYTE_SHIFT 8 292 #define APU_FREQ_HIWORD_SHIFT 0 293 #define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000) 294 295 /* APU register 4 */ 296 #define APUREG_WAVESPACE 4 297 #define APU_STEREO 0x8000 298 #define APU_USE_SYSMEM 0x4000 299 #define APU_PCMBAR_MASK 0x6000 300 #define APU_64KPAGE_MASK 0xff00 301 302 /* PCM Base Address Register selection */ 303 #define APU_PCMBAR_SHIFT 13 304 305 /* 64KW (==128KB) Page */ 306 #define APU_64KPAGE_SHIFT 8 307 308 /* APU register 5 - 7 */ 309 #define APUREG_CURPTR 5 310 #define APUREG_ENDPTR 6 311 #define APUREG_LOOPLEN 7 312 313 /* APU register 9 */ 314 #define APUREG_AMPLITUDE 9 315 #define APU_AMPLITUDE_NOW_MASK 0xff00 316 #define APU_AMPLITUDE_DEST_MASK 0x00ff 317 318 /* Amplitude now? */ 319 #define APU_AMPLITUDE_NOW_SHIFT 8 320 321 /* APU register 10 */ 322 #define APUREG_POSITION 10 323 #define APU_RADIUS_MASK 0x00c0 324 #define APU_PAN_MASK 0x003f 325 326 /* Radius control. */ 327 #define APU_RADIUS_SHIFT 6 328 #define RADIUS_CENTERCIRCLE 0 329 #define RADIUS_MIDDLE 1 330 #define RADIUS_OUTSIDE 2 331 332 /* Polar pan. */ 333 #define APU_PAN_SHIFT 0 334 #define PAN_RIGHT 0x00 335 #define PAN_FRONT 0x08 336 #define PAN_LEFT 0x10 337 338 339 /* ----------------------------- 340 * Limits. 341 */ 342 #define WPWA_MAX ((1 << 22) - 1) 343 #define WPWA_MAXADDR ((1 << 23) - 1) 344 #define MAESTRO_MAXADDR ((1 << 28) - 1) 345 346 #endif /* MAESTRO_REG_H_INCLUDED */ 347