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Searched refs:spill (Results 1 – 25 of 38) sorted by relevance

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/freebsd-head/contrib/llvm-project/compiler-rt/lib/xray/
HDxray_trampoline_powerpc64_asm.S10 # floating point, and vector parameters, so that we only spill those live ones.
151 # floating point, and vector parameters, so that we only spill those live ones.
/freebsd-head/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDSpiller.h31 virtual void spill(LiveRangeEdit &LRE) = 0;
HDRegisterScavenging.h158 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
/freebsd-head/tests/sys/kern/tty/
HDtest_canon_fullbuf.orch21 -- Now fill up the next block, but spill the VEOF over to a third block.
/freebsd-head/contrib/llvm-project/llvm/lib/CodeGen/
HDRegAllocBasic.cpp238 spiller().spill(LRE); in spillInterferences()
298 spiller().spill(LRE); in selectOrSplit()
HDRegisterScavenging.cpp223 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj, in spill() function in RegScavenger
326 ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore); in scavengeRegisterBackwards()
HDInlineSpiller.cpp201 void spill(LiveRangeEdit &) override;
1283 void InlineSpiller::spill(LiveRangeEdit &edit) { in spill() function in InlineSpiller
1648 for (const auto spill : EqValSpills) in hoistAllSpills()
1649 dbgs() << spill->getParent()->getNumber() << " "; in hoistAllSpills()
HDRegAllocFast.cpp383 void spill(MachineBasicBlock::iterator Before, Register VirtReg,
564 void RegAllocFastImpl::spill(MachineBasicBlock::iterator Before, in spill() function in RegAllocFastImpl
1093 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut); in defineVirtReg()
HDRegAllocPBQP.cpp697 VRegSpiller.spill(LRE); in spillVReg()
/freebsd-head/contrib/llvm-project/lld/ELF/
HDLinkerScript.cpp1474 PotentialSpillSection *spill = list.head; in spillSections() local
1475 if (spill->next) in spillSections()
1476 list.head = spill->next; in spillSections()
1486 *llvm::find(spill->isd->sections, spill) = isec; in spillSections()
1487 isec->parent = spill->parent; in spillSections()
1488 isec->addralign = spill->addralign; in spillSections()
/freebsd-head/contrib/llvm-project/llvm/lib/Target/X86/
HDX86FastPreTileConfig.cpp71 void spill(MachineBasicBlock::iterator Before, Register VirtReg, bool Kill);
201 void X86FastPreTileConfig::spill(MachineBasicBlock::iterator Before, in spill() function in X86FastPreTileConfig
624 spill(++MI.getIterator(), TileReg, false); in configBasicBlock()
/freebsd-head/sys/contrib/openzfs/module/zfs/
HDdsl_bookmark.c464 boolean_t spill = B_FALSE; in dsl_bookmark_create_sync_impl_snap() local
472 spill = B_TRUE; in dsl_bookmark_create_sync_impl_snap()
475 DMU_OTN_UINT64_METADATA, spill ? 0 : bonuslen, tx); in dsl_bookmark_create_sync_impl_snap()
478 if (spill) { in dsl_bookmark_create_sync_impl_snap()
487 if (!spill) { in dsl_bookmark_create_sync_impl_snap()
HDdmu_recv.c123 boolean_t spill; /* DRR_FLAG_SPILL_BLOCK set */ member
1940 (!rwa->spill && DRR_OBJECT_HAS_SPILL(drro->drr_flags))) { in receive_object()
2057 dn_slots << DNODE_SHIFT, rwa->spill ? in receive_object()
2059 } else if (rwa->spill && !DRR_OBJECT_HAS_SPILL(drro->drr_flags)) { in receive_object()
2551 if (rwa->spill && DRR_SPILL_IS_UNMODIFIED(drrs->drr_flags)) { in receive_spill()
3415 rwa->spill = drc->drc_spill; in dmu_recv_stream()
HDdmu_send.c1776 uint64_t spill = 0; in send_reader_thread() local
1784 spill = piggyback_unmodified_spill(srta, range); in send_reader_thread()
1789 bqueue_enqueue(outq, range, sizeof (*range) + spill); in send_reader_thread()
/freebsd-head/sys/contrib/openzfs/tests/zfs-tests/tests/functional/channel_program/synctask_core/
HDtst.set_props.zcp36 -- add an extra character so we spill over the limit
/freebsd-head/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcRegisterInfo.td355 // Register class for 64-bit mode, with a 64-bit spill slot size.
358 // spill slot is a stricter constraint than only requiring a 32-bit spill slot.
/freebsd-head/contrib/llvm-project/llvm/lib/Target/M68k/
HDM68kRegisterInfo.td148 // These classes provide spill/restore order if used with MOVEM instruction
HDM68kInstrData.td267 // The mask is already pre-processed by the save/restore spill hook
329 // Pseudo versions. These a required by virtual register spill/restore since
/freebsd-head/contrib/llvm-project/llvm/lib/Target/SystemZ/
HDREADME.txt151 We might want to model all access registers and use them to spill
/freebsd-head/contrib/llvm-project/lld/docs/ELF/
HDlinker_script.rst204 The flag ``--enable-non-contiguous-regions`` allows input sections to spill to
/freebsd-head/contrib/llvm-project/llvm/lib/Target/LoongArch/
HDLoongArchFloat32InstrInfo.td124 // Pseudo instructions for spill/reload CFRs.
/freebsd-head/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMRegisterInfo.td231 // know how to spill them. If we make our prologue/epilogue code smarter at
248 // know how to spill them. If we make our prologue/epilogue code smarter at
HDARMCallingConv.td322 // Also save R7-R4 first to match the stack frame fixed spill areas.
/freebsd-head/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDSIInstrFormats.td49 // Combined SGPR/VGPR spill bit
/freebsd-head/contrib/llvm-project/llvm/include/llvm/Target/
HDTarget.td71 // A class representing the register size, spill size and spill alignment
271 // Size - Specify the spill size in bits of the registers. A default value of

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