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Searched refs:isAfterLegalizeDAG (Results 1 – 8 of 8) sorted by relevance

/freebsd-head/contrib/llvm-project/llvm/lib/Target/VE/
HDVEISelLowering.cpp2802 if (!DCI.isAfterLegalizeDAG()) in combineSelect()
2844 if (!DCI.isAfterLegalizeDAG()) in combineSelectCC()
2998 if (!DCI.isAfterLegalizeDAG()) in combineTRUNCATE()
/freebsd-head/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDTargetLowering.h4225 bool isAfterLegalizeDAG() const { return Level >= AfterLegalizeDAG; } in isAfterLegalizeDAG() function
/freebsd-head/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDSIISelLowering.cpp10190 if ((MemVT.isSimple() && !DCI.isAfterLegalizeDAG()) || in widenLoad()
11225 if (DCI.isAfterLegalizeDAG() && SrcVT == MVT::i32) { in performUCharToFloatCombine()
14201 if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG()) in performAddCombine()
/freebsd-head/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVISelLowering.cpp13720 if (DCI.isAfterLegalizeDAG()) in performANDCombine()
13774 if (DCI.isAfterLegalizeDAG()) in performORCombine()
17322 if (DCI.isAfterLegalizeDAG()) in PerformDAGCombine()
17402 (DCI.isAfterLegalizeDAG() && in PerformDAGCombine()
/freebsd-head/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp20428 if (!DCI.isAfterLegalizeDAG()) in performSVEMulAddSubCombine()
24046 if (DCI.isAfterLegalizeDAG()) in performSetccMergeZeroCombine()
24344 if (VT.is64BitVector() && DCI.isAfterLegalizeDAG()) { in performDUPCombine()
24355 if (DCI.isAfterLegalizeDAG()) { in performDUPCombine()
/freebsd-head/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMISelLowering.cpp15517 if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32 || in PerformExtractEltToVMOVRRD()
18678 if (!DCI.isAfterLegalizeDAG()) in PerformMVETruncCombine()
18844 if (!DCI.isAfterLegalizeDAG()) in PerformMVEExtCombine()
/freebsd-head/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp14039 if (!DCI.isAfterLegalizeDAG()) in ConvertSETCCToSubtract()
16241 if (!DCI.isAfterLegalizeDAG() && Subtarget.hasP9Altivec() && in PerformDAGCombine()
/freebsd-head/contrib/llvm-project/llvm/lib/Target/X86/
HDX86ISelLowering.cpp44665 DCI.isAfterLegalizeDAG() && !LikelyUsedAsVector && LoadVec->isSimple()) { in combineExtractFromVectorLoad()
48273 if (!DCI.isAfterLegalizeDAG()) in combineShiftRightLogical()
48869 if (VT.isSimple() && DCI.isAfterLegalizeDAG()) { in combineVectorInsert()
57500 if (DCI.isAfterLegalizeDAG() && Src.getOpcode() == ISD::FP_ROUND && in combineFP_EXTEND()