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Searched refs:cfg1 (Results 1 – 25 of 31) sorted by relevance

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/freebsd-head/sys/dev/ata/chipsets/
HData-highpoint.c93 if (idx->cfg1 == HPT_374) { in ata_highpoint_probe()
127 if (ctlr->chip->cfg1 < HPT_372) in ata_highpoint_chipinit()
150 if (ctlr->chip->cfg1 == HPT_366) in ata_highpoint_ch_attach()
190 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_highpoint_setmode()
202 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) { in ata_highpoint_check_80pin()
HData-nvidia.c178 if ((ctlr->chip->cfg1 & NVAHCI) && in ata_nvidia_probe()
195 if (ctlr->chip->cfg1 & NVAHCI) { in ata_nvidia_chipinit()
206 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_chipinit()
216 if (ctlr->chip->cfg1 & NVQ) { in ata_nvidia_chipinit()
285 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_status()
286 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); in ata_nvidia_status()
290 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
300 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
HData-sis.c122 id[0].cfg1 = SIS_133NEW; in ata_sis_probe()
136 id[0].cfg1 = SIS_133OLD; in ata_sis_probe()
139 id[0].cfg1 = SIS_100NEW; in ata_sis_probe()
166 switch (ctlr->chip->cfg1) { in ata_sis_chipinit()
246 if (ctlr->chip->cfg1 == SIS_133NEW) { in ata_sis_setmode()
260 switch (ctlr->chip->cfg1) { in ata_sis_setmode()
HData-amd.c96 if (ctlr->chip->cfg1 & AMD_BUG) in ata_amd_chipinit()
121 if (ctlr->chip->cfg1 & AMD_CABLE) { in ata_amd_setmode()
151 if (ctlr->chip->cfg1 & AMD_CABLE) in ata_amd_ch_attach()
HData-serverworks.c130 if (ctlr->chip->cfg1 == SWKS_MIO) { in ata_serverworks_chipinit()
145 else if (ctlr->chip->cfg1 == SWKS_33) { in ata_serverworks_chipinit()
164 ((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1); in ata_serverworks_chipinit()
357 if (ctlr->chip->cfg1 != SWKS_33) { in ata_serverworks_setmode()
HData-intel.c267 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { in ata_intel_chipinit()
289 (ctlr->chip->cfg1 & INTEL_ICH5)) in ata_intel_chipinit()
336 if (ctlr->chip->cfg1 & INTEL_ICH5) { in ata_intel_ch_attach()
352 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { in ata_intel_ch_attach()
374 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { in ata_intel_ch_attach()
378 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { in ata_intel_ch_attach()
431 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) in ata_intel_reset()
HData-ati.c103 switch (ctlr->chip->cfg1) { in ata_ati_probe()
134 if (ctlr->chip->cfg1 == ATI_AHCI) { in ata_ati_chipinit()
HData-via.c248 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
250 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
252 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); in ata_via_ch_attach()
362 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); in ata_via_old_setmode()
HData-jmicron.c112 if (ctlr->chip->cfg1) { in ata_jmicron_chipinit()
HData-marvell.c127 if (ctlr->chip->cfg1) { in ata_marvell_chipinit()
HData-acard.c98 if (ctlr->chip->cfg1 == ATP_OLD) { in ata_acard_chipinit()
HData-promise.c221 switch (ctlr->chip->cfg1) { in ata_promise_chipinit()
364 if (ctlr->chip->cfg1 == PR_NEW) { in ata_promise_ch_attach()
469 switch (ctlr->chip->cfg1) { in ata_promise_setmode()
500 if (ctlr->chip->cfg1 < PR_TX) in ata_promise_setmode()
502 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_promise_setmode()
HData-acerlabs.c113 ctlr->channels = ctlr->chip->cfg1; in ata_ali_chipinit()
HData-siliconimage.c110 switch (ctlr->chip->cfg1) { in ata_sii_chipinit()
/freebsd-head/sys/arm64/freescale/imx/clk/
HDimx_clk_frac_pll.c116 uint32_t cfg0, cfg1; in imx_clk_frac_pll_recalc() local
123 READ4(clk, sc->offset + CFG1, &cfg1); in imx_clk_frac_pll_recalc()
128 divff = (cfg1 & CFG1_FRAC_DIV_MASK) >> CFG1_FRAC_DIV_SHIFT; in imx_clk_frac_pll_recalc()
129 divfi = (cfg1 & CFG1_INT_DIV_MASK) >> CFG1_INT_DIV_SHIFT; in imx_clk_frac_pll_recalc()
/freebsd-head/sys/dev/bhnd/nvram/
HDbhnd_nvram_data_bcmreg.h58 #define BCM_NVRAM_CFG1_SDRAM_CFG_FIELD cfg1
64 #define BCM_NVRAM_CFG1_SDRAM_REFRESH_FIELD cfg1
HDbhnd_nvram_data_bcmvar.h66 uint32_t cfg1; /**< sdram_config:16, sdram_refresh:16 */ member
HDbhnd_nvram_data_bcm.c431 .cfg1 = 0, in bhnd_nvram_bcm_serialize()
440 hdr.cfg1 = BCM_NVRAM_SET_BITS(hdr.cfg1, BCM_NVRAM_CFG1_SDRAM_CFG, in bhnd_nvram_bcm_serialize()
442 hdr.cfg1 = BCM_NVRAM_SET_BITS(hdr.cfg1, BCM_NVRAM_CFG1_SDRAM_REFRESH, in bhnd_nvram_bcm_serialize()
/freebsd-head/sys/contrib/dev/rtw89/
HDpci_be.c411 u32 ctrl0, cfg0, cfg1, dec_ctrl, idle_ltcy, act_ltcy, dis_ltcy; in rtw89_pci_ltr_set_v2() local
419 cfg1 = rtw89_read32(rtwdev, R_BE_LTR_CFG_1); in rtw89_pci_ltr_set_v2()
420 if (rtw89_pci_ltr_is_err_reg_val(cfg1)) in rtw89_pci_ltr_set_v2()
448 cfg1 = u32_replace_bits(cfg1, 0xC0, B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK); in rtw89_pci_ltr_set_v2()
449 cfg1 = u32_replace_bits(cfg1, 0xC0, B_BE_LTR_CMAC1_RX_USE_PG_TH_MASK); in rtw89_pci_ltr_set_v2()
459 rtw89_write32(rtwdev, R_BE_LTR_CFG_1, cfg1); in rtw89_pci_ltr_set_v2()
/freebsd-head/sys/contrib/dev/mediatek/mt76/mt76x2/
HDphy.c187 u32 cfg0, cfg1; in mt76x2_configure_tx_delay() local
191 cfg1 = 0x00011414; in mt76x2_configure_tx_delay()
194 cfg1 = 0x00021414; in mt76x2_configure_tx_delay()
197 mt76_wr(dev, MT_TX_SW_CFG1, cfg1); in mt76x2_configure_tx_delay()
/freebsd-head/sys/dev/qlnx/qlnxe/
HDspad_layout.h205 #define NVM_CFG1(x) g_spad.nvm_cfg.cfg1.x
/freebsd-head/sys/netpfil/ipfw/nat64/
HDnat64lsn_control.c815 #define NAT64LSN_ARE_EQUAL(v) (cfg0->v == cfg1->v)
817 nat64lsn_cmp_configs(struct nat64lsn_cfg *cfg0, struct nat64lsn_cfg *cfg1) in nat64lsn_cmp_configs() argument
820 if ((cfg0->base.flags & cfg1->base.flags & NAT64LSN_ALLOW_SWAPCONF) && in nat64lsn_cmp_configs()
826 &cfg1->base.plat_prefix)) in nat64lsn_cmp_configs()
/freebsd-head/sys/dev/et/
HDif_et.c498 uint32_t cfg1, cfg2, ctrl; in et_miibus_statchg() local
531 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
532 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | in et_miibus_statchg()
563 cfg1 |= ET_MAC_CFG1_TXFLOW; in et_miibus_statchg()
566 cfg1 |= ET_MAC_CFG1_RXFLOW; in et_miibus_statchg()
572 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; in et_miibus_statchg()
573 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); in et_miibus_statchg()
578 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
579 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == in et_miibus_statchg()
/freebsd-head/sys/dev/ata/
HData-pci.h33 int cfg1; member
/freebsd-head/sys/contrib/dev/athk/ath11k/
HDdp.h1573 u32 cfg1; member

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