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Searched refs:asr (Results 1 – 25 of 33) sorted by relevance

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/freebsd-head/contrib/llvm-project/compiler-rt/lib/builtins/arm/
HDdivmodsi4.S52 eor ip, r0, r0, asr #31
53 eor lr, r1, r1, asr #31
54 sub r0, ip, r0, asr #31
55 sub r1, lr, r1, asr #31
60 eor r0, r0, r4, asr #31
61 eor r1, r1, r5, asr #31
62 sub r0, r0, r4, asr #31
63 sub r1, r1, r5, asr #31
HDmodsi3.S45 eor r2, r0, r0, asr #31
46 eor r3, r1, r1, asr #31
47 sub r0, r2, r0, asr #31
48 sub r1, r3, r1, asr #31
52 eor r0, r0, r4, asr #31
53 sub r0, r0, r4, asr #31
HDdivsi3.S61 eor r2, r0, r0, asr #31
62 eor r3, r1, r1, asr #31
63 sub r0, r2, r0, asr #31
64 sub r1, r3, r1, asr #31
74 eor r0, r0, r4, asr #31
75 sub r0, r0, r4, asr #31
HDcomparesf2.S119 mvnlo r0, r1, asr #31
136 movhi r0, r1, asr #31
/freebsd-head/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
HDARMAddressingModes.h29 asr, enumerator
47 case ARM_AM::asr: return "asr"; in getShiftOpcStr()
59 case ARM_AM::asr: return 2; in getShiftOpcEncoding()
HDARMMCCodeEmitter.cpp253 case ARM_AM::asr: return 2; in getShiftOp()
1551 case ARM_AM::asr: SBits = 0x5; break; in getSORegRegOpValue()
1596 case ARM_AM::asr: SBits = 0x4; break; in getSORegImmOpValue()
1703 case ARM_AM::asr: SBits = 0x4; break; in getT2SORegOpValue()
/freebsd-head/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcInstrAliases.td548 def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
554 def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
555 def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;
578 def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
579 def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;
/freebsd-head/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMSelectionDAGInfo.h28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
HDARMFastISel.cpp2643 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 }, in ARMEmitIntExt()
2645 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 }, in ARMEmitIntExt()
2647 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 }, in ARMEmitIntExt()
2889 return SelectShift(I, ARM_AM::asr); in fastSelectInstruction()
HDARMInstrThumb.td1081 "asr", "\t$Rd, $Rm, $imm5",
1092 "asr", "\t$Rdn, $Rm",
1778 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
HDARMInstructionSelector.cpp1073 return selectShift(ARM_AM::ShiftOpc::asr, MIB); in select()
HDARMFeatures.td406 // True if codegen should avoid using flag setting movs with shifter operand (i.e. asr, lsl, lsr).
/freebsd-head/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
HDdffma.S230 TMP = asr(CTMPH,#31)
250 CTMP = asr(CTMP,RIGHTSHIFT)
416 ATMP = asr(ATMP,EXPB)
HDfastmath2_ldlib_asm.S294 mantd = asr(mantd, #30)
HDfastmath2_dlib_asm.S297 mantexpd = asr(mantexpd, #15)
HDfastmath_dlib_asm.S358 lmantc += asr(mantexpd, #15)
HDdfmul.S230 PP_HH = asr(PP_HH,BTMPH)
HDdfsqrt.S297 EXP = asr(EXP,#1) // divide signed exp by 2
/freebsd-head/sys/crypto/openssl/aarch64/
HDaesv8-armx.S1987 and w11,w19,w22,asr#31
2024 and w11,w19,w22,asr#31
2042 and w11,w19,w22,asr#31
2051 and w11,w19,w22,asr#31
2179 and w11,w19,w22,asr#31
2189 and w11,w19,w22,asr#31
2199 and w11,w19,w22,asr#31
2209 and w11,w19,w22,asr#31
2220 and w11,w19,w22,asr #31
2322 and w11,w19,w22,asr#31
[all …]
/freebsd-head/contrib/llvm-project/llvm/lib/Target/M68k/
HDM68kInstrShiftRotate.td95 defm ASR : MxSROp<"asr", sra, MxRODI_R, MxROOP_AS>;
/freebsd-head/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonIntrinsicsV5.td61 //Rxx^=asr(Rss,Rt)
/freebsd-head/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
HDARMAsmParser.cpp641 return parsePKHImm(O, ARM_AM::asr, 1, 32); in parsePKHASRImm()
4285 .Case("asr", ARM_AM::asr) in tryParseShiftToken()
4347 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { in tryParseShiftRegister()
6137 St = ARM_AM::asr; in parseMemRegOffsetShift()
6171 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) in parseMemRegOffsetShift()
10415 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; in processInstruction()
10465 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; in processInstruction()
10497 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; in processInstruction()
10522 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; in processInstruction()
10531 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) in processInstruction()
[all …]
/freebsd-head/sys/crypto/openssl/arm/
HDecp_nistz256-armv4.S2657 adds r4,r4,r3,asr#31
2659 adcs r5,r5,r3,asr#31
2661 adcs r6,r6,r3,asr#31
/freebsd-head/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
HDARMDisassembler.cpp1684 Shift = ARM_AM::asr; in DecodeSORegImmOperand()
1724 Shift = ARM_AM::asr; in DecodeSORegRegOperand()
2122 Opc = ARM_AM::asr; in DecodeAddrMode2IdxInstruction()
2168 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
/freebsd-head/contrib/llvm-project/llvm/lib/Target/ARC/
HDARCInstrInfo.td304 defm ASR : ArcBinaryEXT5Inst<0b000010, "asr">;

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