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Searched refs:XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (Results 1 – 4 of 4) sorted by relevance

/freebsd-head/sys/arm/nvidia/tegra124/
HDtegra124_car.h264 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) macro
HDtegra124_clk_pll.c637 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; in plle_enable()
/freebsd-head/sys/arm64/nvidia/tegra210/
HDtegra210_car.h368 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) macro
HDtegra210_clk_pll.c831 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; in plle_enable()