Searched refs:SrcRegOp (Results 1 – 5 of 5) sorted by relevance
243 const MachineOperand *SrcRegOp = DestSrc->Source; in weightCalcHelper() local244 identityCopy = DestRegOp->getReg() == SrcRegOp->getReg() && in weightCalcHelper()245 DestRegOp->getSubReg() == SrcRegOp->getSubReg(); in weightCalcHelper()
1369 const MachineOperand *SrcRegOp, *DestRegOp; in removeEntryValue() local1370 SrcRegOp = DestSrc->Source; in removeEntryValue()1377 VL.MI.getDebugOperand(0).getReg() == SrcRegOp->getReg()) in removeEntryValue()1848 const MachineOperand *SrcRegOp = DestSrc->Source; in transferRegisterCopy() local1860 Register SrcReg = SrcRegOp->getReg(); in transferRegisterCopy()1893 if (!SrcRegOp->isKill()) in transferRegisterCopy()
2152 const MachineOperand *SrcRegOp = DestSrc->Source; in transferRegisterCopy() local2154 Register SrcReg = SrcRegOp->getReg(); in transferRegisterCopy()2174 if (EmulateOldLDV && !SrcRegOp->isKill()) in transferRegisterCopy()2209 if (TTracker && isCalleeSavedReg(DestReg) && SrcRegOp->isKill()) in transferRegisterCopy()
1098 const MachineOperand *SrcRegOp = DestSrc->Source; in isFullCopyInstr() local1099 return !DestRegOp->getSubReg() && !SrcRegOp->getSubReg(); in isFullCopyInstr()
4450 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUlh() local4451 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUlh()4457 unsigned SrcReg = SrcRegOp.getReg(); in expandUlh()4502 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUsh() local4503 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUsh()4509 unsigned SrcReg = SrcRegOp.getReg(); in expandUsh()4553 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUxw() local4554 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUxw()4560 unsigned SrcReg = SrcRegOp.getReg(); in expandUxw()