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Searched refs:RVV (Results 1 – 11 of 11) sorted by relevance

/freebsd-head/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
HDRISCVCustomBehaviour.cpp250 const RISCVVInversePseudosTable::PseudoInfo *RVV = nullptr; in getSchedClassID() local
254 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW); in getSchedClassID()
257 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW); in getSchedClassID()
259 if (!RVV) in getSchedClassID()
260 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0); in getSchedClassID()
264 if (!RVV) { in getSchedClassID()
280 << " with " << MCII.getName(RVV->Pseudo) << '\n'); in getSchedClassID()
281 return MCII.get(RVV->Pseudo).getSchedClass(); in getSchedClassID()
/freebsd-head/contrib/llvm-project/clang/include/clang/Sema/
HDRISCVIntrinsicManager.h27 enum class IntrinsicKind : uint8_t { RVV, SIFIVE_VECTOR }; enumerator
/freebsd-head/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVAsmPrinter.cpp939 const RISCVVPseudosTable::PseudoInfo *RVV = in lowerRISCVVMachineInstrToMCInst() local
941 if (!RVV) in lowerRISCVVMachineInstrToMCInst()
944 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
HDRISCVInstrInfo.cpp3998 const RISCVVPseudosTable::PseudoInfo *RVV = in getRVVMCOpcode() local
4000 if (!RVV) in getRVVMCOpcode()
4002 return RVV->BaseInstr; in getRVVMCOpcode()
HDRISCVInstrInfoVSDPatterns.td1 //===- RISCVInstrInfoVSDPatterns.td - RVV SDNode patterns --*- tablegen -*-===//
15 /// Note: the patterns for RVV intrinsics are found in
HDRISCVInstrInfoVVLPatterns.td1 //===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===//
15 /// Note: the patterns for RVV intrinsics are found in
/freebsd-head/contrib/llvm-project/clang/lib/Sema/
HDSemaRISCV.cpp85 case IntrinsicKind::RVV: in ProtoSeq2ArrayRef()
358 ConstructRVVIntrinsics(RVVIntrinsicRecords, IntrinsicKind::RVV); in InitIntrinsicList()
/freebsd-head/contrib/llvm-project/clang/include/clang/Basic/
HDriscv_vector_common.td9 // This file defines RVV builtin base class for RISC-V V-extension.
73 // will yield an RVV vector type (assume LMUL=1), so __rvv_int32m1_t.
HDDiagnosticSemaKinds.td3243 "invalid RVV vector size '%0', expected size is '%1' based on LMUL of type "
3246 "%0 attribute applied to non-RVV type %1">;
3365 "cannot combine fixed-length and sizeless %select{SVE|RVV}0 vectors "
3368 …"cannot combine GNU and %select{SVE|RVV}0 vectors in expression, result is ambiguous (%1 and %2)">;
HDAttrDocs.td2461 The attribute can be attached to a single RVV vector (such as ``vint8m1_t``).
/freebsd-head/contrib/llvm-project/clang/include/clang/Driver/
HDOptions.td4857 HelpText<"Specify the size in bits of an RVV vector register">,