Searched refs:NewSrcVT (Results 1 – 3 of 3) sorted by relevance
| /freebsd-head/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeVectorTypes.cpp | 2583 EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx); in SplitVecRes_ExtendOp() local
2587 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT); in SplitVecRes_ExtendOp()
2589 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) { in SplitVecRes_ExtendOp()
2595 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0)); in SplitVecRes_ExtendOp()
2606 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0), in SplitVecRes_ExtendOp()
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| /freebsd-head/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | AMDGPUISelLowering.cpp | 1556 EVT NewSrcVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumSrcElt / 2); in LowerEXTRACT_SUBVECTOR() local
1560 SDValue Tmp = DAG.getNode(ISD::BITCAST, SL, NewSrcVT, Op.getOperand(0)); in LowerEXTRACT_SUBVECTOR()
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| /freebsd-head/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 42987 MVT NewSrcVT = MVT::getIntegerVT(BitWidth / 2); in SimplifyDemandedBitsForTargetNode() local
42989 TLO.DAG.getNode(ISD::TRUNCATE, SDLoc(Src), NewSrcVT, Src); in SimplifyDemandedBitsForTargetNode()
42990 MVT NewVT = MVT::getVectorVT(NewSrcVT, VT.getVectorNumElements() * 2); in SimplifyDemandedBitsForTargetNode()
43801 EVT NewSrcVT = in combineBitcastToBoolVector() local
43803 if (TLI.isTypeLegal(NewSrcVT)) in combineBitcastToBoolVector()
43804 if (SDValue N0 = combineBitcastToBoolVector(NewSrcVT, Src, DL, DAG, in combineBitcastToBoolVector()
43814 EVT NewSrcVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, in combineBitcastToBoolVector() local
43816 if (TLI.isTypeLegal(NewSrcVT)) in combineBitcastToBoolVector()
43817 if (SDValue N0 = combineBitcastToBoolVector(NewSrcVT, Src, DL, DAG, in combineBitcastToBoolVector()
56411 EVT NewSrcVT = SrcVT.getDoubleNumVectorElementsVT(Ctx); in combineConcatVectorOps() local
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