| /freebsd-head/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| HD | HexagonRegisterInfo.cpp | 56 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) in HexagonRegisterInfo() function in HexagonRegisterInfo
61 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(Register R) const { in isEHReturnCalleeSaveReg()
67 HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF, in getCallerSavedRegs()
119 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { in getCalleeSavedRegs()
141 const uint32_t *HexagonRegisterInfo::getCallPreservedMask( in getCallPreservedMask()
147 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) in getReservedRegs()
208 bool HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, in eliminateFrameIndex()
353 bool HexagonRegisterInfo::shouldCoalesce(MachineInstr *MI, in shouldCoalesce()
402 Register HexagonRegisterInfo::getFrameRegister(const MachineFunction in getFrameRegister()
411 Register HexagonRegisterInfo::getFrameRegister() const { in getFrameRegister()
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| HD | HexagonRegisterInfo.h | 29 class HexagonRegisterInfo : public HexagonGenRegisterInfo {
31 HexagonRegisterInfo(unsigned HwMode);
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| HD | HexagonBitTracker.h | 19 class HexagonRegisterInfo; variable
31 HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
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| HD | HexagonFrameLowering.h | 25 class HexagonRegisterInfo; variable
127 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
129 const HexagonRegisterInfo &HRI) const;
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| HD | HexagonVLIWPacketizer.h | 20 class HexagonRegisterInfo; variable
77 const HexagonRegisterInfo *HRI;
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| HD | HexagonISelDAGToDAG.h | 26 class HexagonRegisterInfo; variable
31 const HexagonRegisterInfo *HRI;
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| HD | HexagonSubtarget.h | 104 HexagonRegisterInfo RegInfo;
125 const HexagonRegisterInfo *getRegisterInfo() const override { in getRegisterInfo()
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| HD | HexagonConstExtenders.cpp | 384 const HexagonRegisterInfo *HRI = nullptr;
445 PrintRegister(HCE::Register R, const HexagonRegisterInfo &I) in PrintRegister()
448 const HexagonRegisterInfo &HRI;
461 PrintExpr(const HCE::ExtExpr &E, const HexagonRegisterInfo &I) in PrintExpr()
464 const HexagonRegisterInfo &HRI;
479 PrintInit(const HCE::ExtenderInit &EI, const HexagonRegisterInfo &I) in PrintInit()
482 const HexagonRegisterInfo &HRI;
550 PrintIMap(const HCE::AssignmentMap &M, const HexagonRegisterInfo &I) in PrintIMap()
553 const HexagonRegisterInfo &HRI;
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| HD | HexagonBranchRelaxation.cpp | 70 const HexagonRegisterInfo *HRI;
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| HD | HexagonBitSimplify.cpp | 468 auto &HRI = static_cast<const HexagonRegisterInfo&>( in parseRegSequence()
932 auto &HRI = static_cast<const HexagonRegisterInfo&>( in getFinalVRegClass()
1082 const HexagonRegisterInfo &hri, MachineRegisterInfo &mri) in RedundantInstrElimination()
1098 const HexagonRegisterInfo &HRI;
1535 const HexagonRegisterInfo &hri, MachineRegisterInfo &mri) in CopyGeneration()
1545 const HexagonRegisterInfo &HRI;
1555 CopyPropagation(const HexagonRegisterInfo &hri, MachineRegisterInfo &mri) in CopyPropagation()
1565 const HexagonRegisterInfo &HRI;
1776 const HexagonInstrInfo &hii, const HexagonRegisterInfo &hri, in BitSimplification()
1820 const HexagonRegisterInfo &HRI;
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| HD | HexagonNewValueJump.cpp | 96 const HexagonRegisterInfo *QRI;
460 QRI = static_cast<const HexagonRegisterInfo *>( in runOnMachineFunction()
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| HD | HexagonVectorPrint.cpp | 55 const HexagonRegisterInfo *QRI = nullptr;
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| HD | HexagonPeephole.cpp | 83 const HexagonRegisterInfo *QRI;
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| HD | HexagonGenMux.cpp | 89 const HexagonRegisterInfo *HRI = nullptr;
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| HD | HexagonBitTracker.cpp | 40 HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri, in HexagonEvaluator()
95 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); in mask()
136 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); in composeWithSubRegIndex()
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| HD | HexagonStoreWidening.cpp | 66 const HexagonRegisterInfo *TRI;
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| HD | HexagonGenPredicate.cpp | 109 const HexagonRegisterInfo *TRI = nullptr;
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| HD | HexagonInstrInfo.cpp | 137 static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) { in isDblRegForSubInst()
861 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in copyPhysReg()
1056 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in expandPostRAPseudo()
1733 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in ClobbersPredicate()
2214 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in isDependent()
3926 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getDuplexCandidateGroup()
4330 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getOperandLatency()
4501 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getMemAccessSize()
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| HD | HexagonFrameLowering.cpp | 287 const HexagonRegisterInfo &HRI) { in needsStackFrame()
1361 const CSIVect &CSI, const HexagonRegisterInfo &HRI, in insertCSRSpillsInBlock()
1429 const CSIVect &CSI, const HexagonRegisterInfo &HRI) const { in insertCSRRestoresInBlock()
1527 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) { in needToReserveScavengingSpillSlots()
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| HD | HexagonRegisterInfo.td | 1 //===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
180 // as reserved in HexagonRegisterInfo.cpp.
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| HD | Hexagon.td | 377 include "HexagonRegisterInfo.td"
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| HD | HexagonOptAddrMode.cpp | 86 const HexagonRegisterInfo *HRI = nullptr;
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| HD | HexagonISelLowering.cpp | 460 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerCall()
667 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerINLINEASM()
1187 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerRETURNADDR()
1213 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerFRAMEADDR()
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| HD | HexagonSplitDouble.cpp | 84 const HexagonRegisterInfo *TRI = nullptr;
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| HD | HexagonVLIWPacketizer.cpp | 117 const HexagonRegisterInfo *HRI = nullptr;
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