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/freebsd-head/sys/contrib/device-tree/Bindings/powerpc/fsl/
HDdma.txt1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
13 DMA channels and the address space of the DMA controller
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
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/freebsd-head/sys/contrib/device-tree/Bindings/dma/
HDfsl-imx-dma.txt1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
10 - reg : Should contain DMA registers location and length
11 - interrupts : First item should be DMA interrupt, second one is optional and
12 should contain DMA Error interrupt
16 - dma-channels : Number of DMA channels supported. Should be 16.
18 - dma-requests : Number of DMA requests supported.
32 * DMA client
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HDti-dma-crossbar.txt1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
17 - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
18 when mapping xbar input to DMA request, they are either
23 When requesting channel via ti,dra7-dma-crossbar, the DMA client must request
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Drenesas,shdma.txt3 Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
4 instances, capable of serving any of a common set of DMA slave devices, using
6 SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
7 DMAC instances have the same number of channels and use the same DMA
8 descriptors. Therefore respective DMA DT bindings can also all be placed in the
12 * DMA multiplexer
19 - dma-channels: number of DMA channels
20 - dma-requests: number of DMA request signals
22 * DMA controller
73 * DMA client
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HDmpc512x-dma.txt1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
29 DMA clients must use the format described in dma/dma.txt file.
HDsprd-dma.txt1 * Spreadtrum DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
7 - reg: Should contain DMA registers location and length.
11 - dma-channels : Number of DMA channels supported. Should be 32.
12 - clock-names: Should contain the clock of the DMA controller.
16 - #dma-channels : Number of DMA channels supported. Should be 32.
33 DMA clients connected to the Spreadtrum DMA controller must use the format
36 1. A phandle pointing to the DMA controller.
HDmmp-dma.txt1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - dma-channels: Number of DMA channels supported by the controller (defaults
16 - dma-requests: Number of DMA requestor lines supported by the controller
28 * while DMA controller may not able to distinguish the irq channel
43 * Dmaengine driver (DMA controller) distinguish irq channel via
54 Marvell Two Channel DMA Controller used specifically for audio
59 - reg: Should contain DMA registers location and length.
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HDowl-dma.txt1 * Actions Semi Owl SoCs DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
7 - reg: Should contain DMA registers location and length.
12 - dma-requests: Number of DMA request signals supported by the controller.
14 - clocks: Phandle and Specifier of the clock feeding the DMA controller.
34 DMA clients connected to the Actions Semi Owl SoCs DMA controller must
39 1. A phandle pointing to the DMA controller.
HDapm-xgene-dma.txt1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
6 Required properties for DMA interfaces:
11 1st - DMA control and status register address space.
15 - interrupts: DMA has 5 interrupts sources. 1st interrupt is
16 DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
17 are completion interrupts for each DMA channels.
HDatmel-dma.txt1 * Atmel Direct Memory Access Controller (DMA)
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain DMA interrupt.
19 DMA clients connected to the Atmel DMA controller must use the format
24 1. A phandle pointing to the DMA controller.
27 3. Parameters for the at91 DMA configuration register which are device
Dadi,axi-dmac.txt1 Analog Devices AXI-DMAC DMA controller
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
31 - adi,length-width: Width of the DMA transfer length register.
32 - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
34 - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
36 DMA clients connected to the AXI-DMAC DMA controller must use the format
38 specifier refers to the DMA channel index.
HDmilbeaut-m10v-xdmac.txt1 * Milbeaut AXI DMA Controller
3 Milbeaut AXI DMA controller has only memory to memory transfer capability.
5 * DMA controller
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain all of the per-channel DMA interrupts.
Dnvidia,tegra20-apbdma.txt1 * NVIDIA Tegra APB DMA controller
5 - reg: Should contain DMA registers location and length. This should include
7 - interrupts: Should contain all of the per-channel DMA interrupts.
14 - #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
15 client nodes' dmas properties. The specifier represents the DMA request
17 documentation of the APB DMA channel control register REQ_SEL field.
Dbrcm,bcm2835-dma.txt1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
70 DMA clients connected to the BCM2835 DMA controller must use the format
HDlpc1850-dmamux.txt1 NXP LPC18xx/43xx DMA MUX (DMA request router)
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
HDfsl-mxs-dma.txt1 * Freescale MXS DMA
6 - interrupts : Should contain the interrupt numbers of DMA channels.
9 - dma-channels : Number of channels supported by the DMA controller
12 - interrupt-names : Name of DMA channel interrupts
49 DMA clients connected to the MXS DMA controller must use the format
HDste-dma40.txt1 * DMA40 DMA Controller
37 1. A phandle pointing to the DMA controller
40 3. The DMA request line number (only when 'use fixed channel' is set)
54 Use DMA request line number when set
113 51: memcpy TX (to be used by the DMA driver for memcpy operations)
118 56: memcpy (to be used by the DMA driver for memcpy operations)
119 57: memcpy (to be used by the DMA driver for memcpy operations)
120 58: memcpy (to be used by the DMA driver for memcpy operations)
121 59: memcpy (to be used by the DMA driver for memcpy operations)
122 60: memcpy (to be used by the DMA driver for memcpy operations)
HDimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
6 - interrupts: Must contain all the per-channel DMA interrupts.
12 node which contains the DMA request to channel mapping registers.
17 - The first cell is the peripheral's DMA request line.
18 - The second cell is a bitmap specifying to which channels the DMA request
23 - dma-channels: Number of supported DMA channels, up to 32. If not specified
/freebsd-head/sys/contrib/device-tree/Bindings/soc/ti/
HDkeystone-navigator-dma.txt1 Keystone Navigator DMA Controller
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
34 into DMA and the DMA uses it as the physical addresses to reach queue
36 they are relevant only from DMA perspective. The QMSS may not choose to
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/freebsd-head/sys/contrib/device-tree/Bindings/powerpc/4xx/
HDppc440spe-adma.txt1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
4 are specified hereby. These are I2O/DMA, DMA and XOR nodes
5 for DMA engines and Memory Queue Module node. The latter is used
9 DMA devices.
28 ii) The DMA node
33 - cell-index : 1 cell, hardware index of the DMA engine
39 and DMA Error IRQ (on UIC1). The latter is common
40 for both DMA engines>.
/freebsd-head/sys/contrib/device-tree/Bindings/spi/
HDomap-spi.txt15 - dmas: List of DMA specifiers with the controller specific format
16 as described in the generic DMA client binding. A tx and rx
18 - dma-names: List of DMA request names. These strings correspond
19 1:1 with the DMA specifiers listed in dmas. The string naming
25 [hwmod populated DMA resources]
35 [generic DMA request binding]
/freebsd-head/sys/contrib/device-tree/Bindings/sound/
Dfsl,ssi.txt35 - fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to
56 - fsl,playback-dma: Phandle to a node for the DMA channel to use for
60 - fsl,capture-dma: Phandle to a node for the DMA channel to use for
74 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
75 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
76 playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
77 playback and DMA channel 3 for capture. The developer can choose which
78 DMA controller to use, but the channels themselves are hard-wired. The
81 The device tree nodes for the DMA channels that are referenced by
85 "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
HDsprd-pcm.txt1 * Spreadtrum DMA platform bindings
5 - dmas: Specify the list of DMA controller phandle and DMA request line ordered pairs.
6 - dma-names: Identifier string for each DMA request line in the dmas property.
/freebsd-head/sys/contrib/device-tree/Bindings/mips/cavium/
HDdma-engine.txt1 * DMA Engine.
3 The Octeon DMA Engine transfers between the Boot Bus and main memory.
4 The DMA Engine will be referred to by phandle by any device that is
12 - reg: The base address of the DMA Engine's register bank.
/freebsd-head/sys/contrib/device-tree/Bindings/crypto/
HDatmel-crypto.txt11 - dmas: List of two DMA specifiers as described in
13 - dma-names: Contains one identifier string for each DMA specifier
33 - dmas: List of two DMA specifiers as described in
35 - dma-names: Contains one identifier string for each DMA specifier
56 - dmas: One DMA specifiers as described in
58 - dma-names: Contains one identifier string for each DMA specifier

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