Searched refs:Control (Results 1 – 25 of 358) sorted by relevance
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202 if (WalkState->ControlState->Control.AmlPredicateStart == in AcpiDsExecBeginControlOp()231 ControlState->Control.AmlPredicateStart = in AcpiDsExecBeginControlOp()233 ControlState->Control.PackageEnd = in AcpiDsExecBeginControlOp()235 ControlState->Control.Opcode = in AcpiDsExecBeginControlOp()237 ControlState->Control.LoopTimeout = AcpiOsGetTimer () + in AcpiDsExecBeginControlOp()337 ControlState->Control.LoopTimeout)) in AcpiDsExecEndControlOp()349 ControlState->Control.AmlPredicateStart; in AcpiDsExecEndControlOp()486 (WalkState->ControlState->Control.Opcode != AML_WHILE_OP)) in AcpiDsExecEndControlOp()502 WalkState->ControlState->Control.PackageEnd; in AcpiDsExecEndControlOp()
12 tcs-bin 5 TCS-BIN # Telephony Control Specification13 tcs-bin-cordless 7 TCS-BIN-CORDLESS # Telephony Control Specification15 hid-control 17 HID-Control # Human Interface Device (control)18 avctp 23 AVCTP # Audio/Video Control Transport Protocol
26 hp-cfg[0]: HPSEL[1:0] of R48 (Additional Control 4).27 hp-cfg[1]: {HPSWEN:HPSWPOL} of R24 (Additional Control 2).28 hp-cfg[2]: {TOCLKSEL:TOEN} of R23 (Additional Control 1).33 gpio-cfg[1]: {GPIOPOL:GPIOSEL[2:0]} of R48 (Additional Control 4).
10 - add-ctrl: Default register value for Reg-40h, Additional Control15 Control Register. If absent or has value 0, the
16 of R51 (Class D Control 2) gets set, indicating that the speaker is19 - mic-cfg : Default register value for R48 (Additional Control 4).
84 Section 7.29 Class H Control89 Section 7.30 Class H Headroom Control95 Section 7.32 Class H Weak FET Drive Control100 Section 7.34 Class H VP Control111 See Sections 4.8.2 through 4.8.4 Serial-Port Control in the Datasheet
4 @settitle ntpdc: NTPD Control User's Manual15 * ntpdc: (ntpdc). ntpd Control program19 @title ntpdc: NTPD Control User's Manual28 @top ntpdc: NTPD Control User Manual
1 OMAP Control Module bindings3 Control Module contains miscellaneous features under it based on SoC type.30 - reg: Contains Control Module register address range
46 0x80 System Control98 0x20 Flight Control Stick100 0x22 Cyclic Control103 0x25 Track Control107 0xB2 Anti-Torque Control110 0xB5 Collective Control222 6 Generic Device Control227 0x23 Discover Wireless Control611 0x01 Consumer Control731 0x104 Climate Control Enable[all …]
55 0x0a "Control" {84 0x0a,0x01 "Control Extension" {164 0x1c,0x01 "Background Control" {178 0x0a,0x06 "Background Operation Control" {259 0x1c "Informational Exceptions Control" {295 0x0a,0xf1 "PATA Control";350 0x0E "CD-ROM Audio Control Parameters" {387 {Automatic Velocity Control} t1
1 * ARM Snoop Control Unit (SCU)4 with a Snoop Control Unit. The register range is usually 256 (0x100)
19 Control 0 register. This will cover that register, as well as the20 Core PLL and Clock Divider Control 1 register. Thus, it will have
4 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)36 Peripheral Clock Control (PCC) modules:38 The Peripheral Clock Control (PCC) is responsible for clock selection,
2 UFS Access Control Lists Copyright4 The UFS Access Control Lists implementation is copyright Robert Watson,7 About UFS Access Control Lists (ACLs)16 Using UFS Access Control Lists (ACLs)
86 IN UINT32 Control93 OUT UINT32 *Control
240 * Host Control Register348 * Queue Offset Control & Status376 * Interrupt Control392 * Data FIFO Control465 * Arbiter Control613 * ROM Control795 * PCI-X Control1440 * LQ Manager Control 01453 * LQ Manager Control 11465 * LQ Manager Control 2[all …]
334 WalkState->ControlState->Control.PackageEnd = in AcpiPsGetArguments()555 ((WalkState->ControlState->Control.Opcode == AML_IF_OP) || in AcpiPsParseLoop()556 (WalkState->ControlState->Control.Opcode == AML_WHILE_OP))) in AcpiPsParseLoop()563 WalkState->ControlState->Control.AmlPredicateStart + 1; in AcpiPsParseLoop()
119 Control = x86_32_Flag | 0x00000001, enumerator127 Full = Control | Integer | Segments,
11 - Output Level Control12 - Output Three-State Control
21 - fsl,dmacr: DMA Control Register value. This is optional. By default, the23 - fsl,lpccr: Contrast Control Register value. This property provides the
18 - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in19 the SCFG or the External Interrupt Control Register (IRQCR) in
50 ftp 21/tcp #File Transfer [Control]51 ftp 21/udp #File Transfer [Control]52 ftp 21/sctp #File Transfer [Control]177 dcp 93/tcp #Device Control Protocol178 dcp 93/udp #Device Control Protocol270 emfis-cntl 141/tcp #EMFIS Control Service271 emfis-cntl 141/udp #EMFIS Control Service342 xdmcp 177/tcp #X Display Manager Control Protocol343 xdmcp 177/udp #X Display Manager Control Protocol369 gacp 190/tcp #Gateway Access Control Protocol[all …]
49 * channels are connecting to 4 Fan Control Boards.229 * PCA9548 (32-0070), 8 channels connecting to Fan Control242 * PCA9548 (33-0070), 8 channels connecting to Fan Control255 * PCA9548 (34-0070), 8 channels connecting to Fan Control268 * PCA9548 (35-0070), 8 channels connecting to Fan Control1279 * I2C bus to Fan Control Boards.1291 /* To Fan Control Board #1 */1347 /* To Fan Control Board #2 */1403 /* To Fan Control Board #3 */1459 /* To Fan Control Board #4 */
39 dccp 33 DCCP # Datagram Congestion Control Protocol44 idpr-cmtp 38 IDPR-CMTP # IDPR Control Message Transport Proto102 micp 95 MICP # Mobile Internetworking Control Pro.139 sctp 132 SCTP # Stream Control Transmission Protocol
3 Stream Control Transmission Protocol