Searched refs:CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT (Results 1 – 2 of 2) sorted by relevance
60 #define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT 6 macro
460 reg |= (CHSCCDR_IPU_PRE_CLK_PLL5 << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT); in imx_ccm_ipu_enable()