Searched refs:Banks (Results 1 – 17 of 17) sorted by relevance
113 const std::vector<RegisterBank> &Banks);115 const std::vector<RegisterBank> &Banks);117 std::vector<RegisterBank> &Banks);131 const std::vector<RegisterBank> &Banks) { in emitHeader() argument139 for (const auto &Bank : Banks) in emitHeader()150 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument217 raw_ostream &OS, StringRef TargetName, std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument223 for (const auto &Bank : Banks) { in emitBaseClassImplementation()246 for (const auto &Bank : Banks) { in emitBaseClassImplementation()260 for (const auto &Bank : Banks) in emitBaseClassImplementation()[all …]
1 //=- ARMRegisterBank.td - Describe the AArch64 Banks ---------*- tablegen -*-=//
1 //===-- BPFRegisterBanks.td - Describe the BPF Banks -------*- tablegen -*-===//
1 //=-- RISCVRegisterBank.td - Describe the RISC-V Banks -------*- tablegen -*-=//
1 //===-- M68kRegisterBanks.td - Describe the M68k Banks -----*- tablegen -*-===//
1 //=- X86RegisterBank.td - Describe the X86 Banks -------------*- tablegen -*-=//
1 //=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
1 //===-- PPCRegisterBanks.td - Describe the PPC Banks -------*- tablegen -*-===//
1 //=- AMDGPURegisterBank.td - Describe the AMDGPU Banks -------*- tablegen -*-=//
56 Banks layout of xsphy
17 The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
138 o make event_rpcgen.py generate code include event-config.h; reported by Sam Banks.
1190 o make event_rpcgen.py generate code include event-config.h; reported by Sam Banks.
283 Shared Data Banks . . . . . . . . . . . 377--387
1930 title = "A Relational Model of Data for Large Shared Data Banks",