Home
last modified time | relevance | path

Searched refs:AArch64 (Results 1 – 25 of 153) sorted by relevance

1234567

/freebsd-head/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
HDAArch64BaseInfo.h32 case AArch64::X0: return AArch64::W0; in getWRegFromXReg()
33 case AArch64::X1: return AArch64::W1; in getWRegFromXReg()
34 case AArch64::X2: return AArch64::W2; in getWRegFromXReg()
35 case AArch64::X3: return AArch64::W3; in getWRegFromXReg()
36 case AArch64::X4: return AArch64::W4; in getWRegFromXReg()
37 case AArch64::X5: return AArch64::W5; in getWRegFromXReg()
38 case AArch64::X6: return AArch64::W6; in getWRegFromXReg()
39 case AArch64::X7: return AArch64::W7; in getWRegFromXReg()
40 case AArch64::X8: return AArch64::W8; in getWRegFromXReg()
41 case AArch64::X9: return AArch64::W9; in getWRegFromXReg()
[all …]
/freebsd-head/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64MacroFusion.cpp24 if (SecondMI.getOpcode() != AArch64::Bcc) in isArithmeticBccPair()
34 !(FirstMI->getOperand(0).getReg() == AArch64::XZR || in isArithmeticBccPair()
35 FirstMI->getOperand(0).getReg() == AArch64::WZR)) { in isArithmeticBccPair()
40 case AArch64::ADDSWri: in isArithmeticBccPair()
41 case AArch64::ADDSWrr: in isArithmeticBccPair()
42 case AArch64::ADDSXri: in isArithmeticBccPair()
43 case AArch64::ADDSXrr: in isArithmeticBccPair()
44 case AArch64::ANDSWri: in isArithmeticBccPair()
45 case AArch64::ANDSWrr: in isArithmeticBccPair()
46 case AArch64::ANDSXri: in isArithmeticBccPair()
[all …]
HDAArch64FalkorHWPFFix.cpp244 case AArch64::LD1i64: in getLoadInfo()
245 case AArch64::LD2i64: in getLoadInfo()
252 case AArch64::LD1i8: in getLoadInfo()
253 case AArch64::LD1i16: in getLoadInfo()
254 case AArch64::LD1i32: in getLoadInfo()
255 case AArch64::LD2i8: in getLoadInfo()
256 case AArch64::LD2i16: in getLoadInfo()
257 case AArch64::LD2i32: in getLoadInfo()
258 case AArch64::LD3i8: in getLoadInfo()
259 case AArch64::LD3i16: in getLoadInfo()
[all …]
HDAArch64InstrInfo.cpp83 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP, in AArch64InstrInfo()
84 AArch64::CATCHRET), in AArch64InstrInfo()
97 if (Op == AArch64::INLINEASM || Op == AArch64::INLINEASM_BR) in getInstSizeInBytes()
157 case AArch64::SPACE: in getInstSizeInBytes()
185 case AArch64::Bcc: in parseCondBranch()
189 case AArch64::CBZW: in parseCondBranch()
190 case AArch64::CBZX: in parseCondBranch()
191 case AArch64::CBNZW: in parseCondBranch()
192 case AArch64::CBNZX: in parseCondBranch()
198 case AArch64::TBZW: in parseCondBranch()
[all …]
HDAArch64DeadRegisterDefinitionsPass.cpp79 case AArch64::LDADDB: case AArch64::LDADDH: in atomicReadDroppedOnZero()
80 case AArch64::LDADDW: case AArch64::LDADDX: in atomicReadDroppedOnZero()
81 case AArch64::LDADDLB: case AArch64::LDADDLH: in atomicReadDroppedOnZero()
82 case AArch64::LDADDLW: case AArch64::LDADDLX: in atomicReadDroppedOnZero()
83 case AArch64::LDCLRB: case AArch64::LDCLRH: in atomicReadDroppedOnZero()
84 case AArch64::LDCLRW: case AArch64::LDCLRX: in atomicReadDroppedOnZero()
85 case AArch64::LDCLRLB: case AArch64::LDCLRLH: in atomicReadDroppedOnZero()
86 case AArch64::LDCLRLW: case AArch64::LDCLRLX: in atomicReadDroppedOnZero()
87 case AArch64::LDEORB: case AArch64::LDEORH: in atomicReadDroppedOnZero()
88 case AArch64::LDEORW: case AArch64::LDEORX: in atomicReadDroppedOnZero()
[all …]
HDAArch64SIMDInstrOpt.cpp104 RuleST2(AArch64::ST2Twov2d, AArch64::ZIP1v2i64, AArch64::ZIP2v2i64,
105 AArch64::STPQi, AArch64::FPR128RegClass),
106 RuleST2(AArch64::ST2Twov4s, AArch64::ZIP1v4i32, AArch64::ZIP2v4i32,
107 AArch64::STPQi, AArch64::FPR128RegClass),
108 RuleST2(AArch64::ST2Twov2s, AArch64::ZIP1v2i32, AArch64::ZIP2v2i32,
109 AArch64::STPDi, AArch64::FPR64RegClass),
110 RuleST2(AArch64::ST2Twov8h, AArch64::ZIP1v8i16, AArch64::ZIP2v8i16,
111 AArch64::STPQi, AArch64::FPR128RegClass),
112 RuleST2(AArch64::ST2Twov4h, AArch64::ZIP1v4i16, AArch64::ZIP2v4i16,
113 AArch64::STPDi, AArch64::FPR64RegClass),
[all …]
HDAArch64CondBrTuning.cpp94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV) in convertToFlagSetting()
101 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in convertToFlagSetting()
118 case AArch64::CBZW: in convertToCondBr()
119 case AArch64::CBZX: in convertToCondBr()
122 case AArch64::CBNZW: in convertToCondBr()
123 case AArch64::CBNZX: in convertToCondBr()
126 case AArch64::TBZW: in convertToCondBr()
127 case AArch64::TBZX: in convertToCondBr()
130 case AArch64::TBNZW: in convertToCondBr()
131 case AArch64::TBNZX: in convertToCondBr()
[all …]
HDAArch64ExpandPseudoInsts.cpp134 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) { in expandMOVImm()
152 case AArch64::ORRWri: in expandMOVImm()
153 case AArch64::ORRXri: in expandMOVImm()
157 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR) in expandMOVImm()
171 case AArch64::ORRWrs: in expandMOVImm()
172 case AArch64::ORRXrs: { in expandMOVImm()
184 case AArch64::ANDXri: in expandMOVImm()
185 case AArch64::EORXri: in expandMOVImm()
189 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR) in expandMOVImm()
203 case AArch64::MOVNWi: in expandMOVImm()
[all …]
HDAArch64PBQPRegAlloc.cpp40 case AArch64::S1: in isOdd()
41 case AArch64::S3: in isOdd()
42 case AArch64::S5: in isOdd()
43 case AArch64::S7: in isOdd()
44 case AArch64::S9: in isOdd()
45 case AArch64::S11: in isOdd()
46 case AArch64::S13: in isOdd()
47 case AArch64::S15: in isOdd()
48 case AArch64::S17: in isOdd()
49 case AArch64::S19: in isOdd()
[all …]
HDAArch64LoadStoreOptimizer.cpp227 case AArch64::STRBBui: in isNarrowStore()
228 case AArch64::STURBBi: in isNarrowStore()
229 case AArch64::STRHHui: in isNarrowStore()
230 case AArch64::STURHHi: in isNarrowStore()
241 case AArch64::STGi: in isTagStore()
242 case AArch64::STZGi: in isTagStore()
243 case AArch64::ST2Gi: in isTagStore()
244 case AArch64::STZ2Gi: in isTagStore()
258 case AArch64::STRDui: in getMatchingNonSExtOpcode()
259 case AArch64::STURDi: in getMatchingNonSExtOpcode()
[all …]
HDAArch64AsmPrinter.cpp382 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8)); in emitSled()
385 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); in emitSled()
411 MCInst MovX0Op0 = MCInstBuilder(AArch64::ORRXrs) in LowerPATCHABLE_EVENT_CALL()
412 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
413 .addReg(AArch64::XZR) in LowerPATCHABLE_EVENT_CALL()
416 MCInst MovX1Op1 = MCInstBuilder(AArch64::ORRXrs) in LowerPATCHABLE_EVENT_CALL()
417 .addReg(AArch64::X1) in LowerPATCHABLE_EVENT_CALL()
418 .addReg(AArch64::XZR) in LowerPATCHABLE_EVENT_CALL()
429 EmitToStreamer(O, MCInstBuilder(AArch64::B).addImm(9)); in LowerPATCHABLE_EVENT_CALL()
430 EmitToStreamer(O, MCInstBuilder(AArch64::STPXpre) in LowerPATCHABLE_EVENT_CALL()
[all …]
HDAArch64CallingConvention.cpp23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
24 AArch64::X3, AArch64::X4, AArch64::X5,
25 AArch64::X6, AArch64::X7};
26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
27 AArch64::H3, AArch64::H4, AArch64::H5,
28 AArch64::H6, AArch64::H7};
29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
30 AArch64::S3, AArch64::S4, AArch64::S5,
31 AArch64::S6, AArch64::S7};
32 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
[all …]
HDAArch64ISelDAGToDAG.cpp767 NewShiftOp = VT == MVT::i64 ? AArch64::UBFMXri : AArch64::UBFMWri; in SelectShiftedRegisterFromAnd()
786 NewShiftOp = VT == MVT::i64 ? AArch64::UBFMXri : AArch64::UBFMWri; in SelectShiftedRegisterFromAnd()
788 NewShiftOp = VT == MVT::i64 ? AArch64::SBFMXri : AArch64::SBFMWri; in SelectShiftedRegisterFromAnd()
915 return CurDAG->getTargetExtractSubreg(AArch64::sub_32, dl, MVT::i32, N); in narrowIfNeeded()
1195 return CurDAG->getTargetInsertSubreg(AArch64::sub_32, dl, MVT::i64, ImpDef, in Widen()
1363 CurDAG->getMachineNode(AArch64::MOVi64imm, DL, MVT::i64, Ops); in SelectAddrModeXRO()
1399 AArch64::DDRegClassID, AArch64::DDDRegClassID, AArch64::DDDDRegClassID}; in createDTuple()
1400 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple()
1401 AArch64::dsub2, AArch64::dsub3}; in createDTuple()
1408 AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID}; in createQTuple()
[all …]
HDAArch64StackTaggingPreRA.cpp103 case AArch64::LDRBBui: in isUncheckedLoadOrStoreOpcode()
104 case AArch64::LDRHHui: in isUncheckedLoadOrStoreOpcode()
105 case AArch64::LDRWui: in isUncheckedLoadOrStoreOpcode()
106 case AArch64::LDRXui: in isUncheckedLoadOrStoreOpcode()
108 case AArch64::LDRBui: in isUncheckedLoadOrStoreOpcode()
109 case AArch64::LDRHui: in isUncheckedLoadOrStoreOpcode()
110 case AArch64::LDRSui: in isUncheckedLoadOrStoreOpcode()
111 case AArch64::LDRDui: in isUncheckedLoadOrStoreOpcode()
112 case AArch64::LDRQui: in isUncheckedLoadOrStoreOpcode()
114 case AArch64::LDRSHWui: in isUncheckedLoadOrStoreOpcode()
[all …]
HDAArch64CollectLOH.cpp176 case AArch64::ADRP: in canDefBePartOfLOH()
178 case AArch64::ADDXri: in canDefBePartOfLOH()
180 case AArch64::LDRXui: in canDefBePartOfLOH()
181 case AArch64::LDRWui: in canDefBePartOfLOH()
198 case AArch64::STRBBui: in isCandidateStore()
199 case AArch64::STRHHui: in isCandidateStore()
200 case AArch64::STRBui: in isCandidateStore()
201 case AArch64::STRHui: in isCandidateStore()
202 case AArch64::STRWui: in isCandidateStore()
203 case AArch64::STRXui: in isCandidateStore()
[all …]
HDAArch64FrameLowering.cpp366 if (Reg == AArch64::LR) { in homogeneousPrologEpilog()
367 assert(CSRegs[I + 1] == AArch64::FP); in homogeneousPrologEpilog()
372 if (AArch64::GPR64RegClass.contains(Reg)) in homogeneousPrologEpilog()
400 MI.getOpcode() == AArch64::ADDXri || in estimateRSStackSizeLimit()
401 MI.getOpcode() == AArch64::ADDSXri) in estimateRSStackSizeLimit()
562 -Amount >= AArch64::StackProbeMaxUnprobedStack) { in eliminateCallFramePseudoInstr()
572 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateCallFramePseudoInstr()
575 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, in eliminateCallFramePseudoInstr()
583 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, in eliminateCallFramePseudoInstr()
621 DwarfReg == TRI.getDwarfRegNum(AArch64::VG, true))) in emitCalleeSavedGPRLocations()
[all …]
HDAArch64FastISel.cpp362 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca()
363 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::ADDXri), in fastMaterializeAlloca()
382 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
383 : &AArch64::GPR32RegClass; in materializeInt()
384 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt()
407 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; in materializeFP()
413 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP()
415 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
434 Register ADRPReg = createResultReg(&AArch64::GPR64commonRegClass); in materializeFP()
435 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::ADRP), in materializeFP()
[all …]
HDAArch64ConditionalCompares.cpp259 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in isDeadDef()
284 case AArch64::CBZW: in parseCond()
285 case AArch64::CBZX: in parseCond()
289 case AArch64::CBNZW: in parseCond()
290 case AArch64::CBNZX: in parseCond()
302 if (!I->readsRegister(AArch64::NZCV, /*TRI=*/nullptr)) { in findConvertibleCompare()
304 case AArch64::CBZW: in findConvertibleCompare()
305 case AArch64::CBZX: in findConvertibleCompare()
306 case AArch64::CBNZW: in findConvertibleCompare()
307 case AArch64::CBNZX: in findConvertibleCompare()
[all …]
HDAArch64RegisterInfo.cpp43 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) { in AArch64RegisterInfo()
54 if (AArch64::PPRRegClass.contains(Reg)) in regNeedsCFI()
57 if (AArch64::ZPRRegClass.contains(Reg)) { in regNeedsCFI()
58 RegToUseForCFI = getSubReg(Reg, AArch64::dsub); in regNeedsCFI()
219 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) { in UpdateCustomCalleeSavedRegs()
221 UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i)); in UpdateCustomCalleeSavedRegs()
233 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
234 return &AArch64::FPR32RegClass; in getSubClassWithSubReg()
235 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
236 return &AArch64::FPR64RegClass; in getSubClassWithSubReg()
[all …]
/freebsd-head/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
HDAArch64InstPrinter.cpp82 if (Opcode == AArch64::SYSxt) in printInst()
88 if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) in printInst()
95 if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) { in printInst()
101 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || in printInst()
102 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { in printInst()
108 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); in printInst()
109 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); in printInst()
153 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
156 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
160 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
[all …]
HDAArch64MCTargetDesc.cpp55 CPU = AArch64::resolveCPUAlias(CPU); in createAArch64MCSubtargetInfo()
75 {codeview::RegisterId::ARM64_W0, AArch64::W0}, in initLLVMToCVRegMapping()
76 {codeview::RegisterId::ARM64_W1, AArch64::W1}, in initLLVMToCVRegMapping()
77 {codeview::RegisterId::ARM64_W2, AArch64::W2}, in initLLVMToCVRegMapping()
78 {codeview::RegisterId::ARM64_W3, AArch64::W3}, in initLLVMToCVRegMapping()
79 {codeview::RegisterId::ARM64_W4, AArch64::W4}, in initLLVMToCVRegMapping()
80 {codeview::RegisterId::ARM64_W5, AArch64::W5}, in initLLVMToCVRegMapping()
81 {codeview::RegisterId::ARM64_W6, AArch64::W6}, in initLLVMToCVRegMapping()
82 {codeview::RegisterId::ARM64_W7, AArch64::W7}, in initLLVMToCVRegMapping()
83 {codeview::RegisterId::ARM64_W8, AArch64::W8}, in initLLVMToCVRegMapping()
[all …]
HDAArch64AsmBackend.cpp48 return AArch64::NumTargetFixupKinds; in getNumFixupKinds()
54 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = { in getFixupKindInfo()
122 case AArch64::fixup_aarch64_movw: in getFixupKindNumBytes()
123 case AArch64::fixup_aarch64_pcrel_branch14: in getFixupKindNumBytes()
124 case AArch64::fixup_aarch64_pcrel_branch16: in getFixupKindNumBytes()
125 case AArch64::fixup_aarch64_add_imm12: in getFixupKindNumBytes()
126 case AArch64::fixup_aarch64_ldst_imm12_scale1: in getFixupKindNumBytes()
127 case AArch64::fixup_aarch64_ldst_imm12_scale2: in getFixupKindNumBytes()
128 case AArch64::fixup_aarch64_ldst_imm12_scale4: in getFixupKindNumBytes()
129 case AArch64::fixup_aarch64_ldst_imm12_scale8: in getFixupKindNumBytes()
[all …]
/freebsd-head/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
HDAArch64Disassembler.cpp256 case AArch64::MPRRegClassID: in getInstruction()
257 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA)); in getInstruction()
259 case AArch64::MPR8RegClassID: in getInstruction()
260 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0)); in getInstruction()
262 case AArch64::ZTRRegClassID: in getInstruction()
263 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0)); in getInstruction()
267 AArch64::OPERAND_IMPLICIT_IMM_0) { in getInstruction()
272 if (MI.getOpcode() == AArch64::LDR_ZA || in getInstruction()
273 MI.getOpcode() == AArch64::STR_ZA) { in getInstruction()
352 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister( in DecodeGPR64x8ClassRegisterClass()
[all …]
/freebsd-head/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
HDAArch64PostSelectOptimize.cpp71 case AArch64::SUBSXrr: in getNonFlagSettingVariant()
72 return AArch64::SUBXrr; in getNonFlagSettingVariant()
73 case AArch64::SUBSWrr: in getNonFlagSettingVariant()
74 return AArch64::SUBWrr; in getNonFlagSettingVariant()
75 case AArch64::SUBSXrs: in getNonFlagSettingVariant()
76 return AArch64::SUBXrs; in getNonFlagSettingVariant()
77 case AArch64::SUBSWrs: in getNonFlagSettingVariant()
78 return AArch64::SUBWrs; in getNonFlagSettingVariant()
79 case AArch64::SUBSXri: in getNonFlagSettingVariant()
80 return AArch64::SUBXri; in getNonFlagSettingVariant()
[all …]
/freebsd-head/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
HDAArch64AsmParser.cpp97 case AArch64::MOVPRFX_ZZ: in CreateFromInst()
101 case AArch64::MOVPRFX_ZPmZ_B: in CreateFromInst()
102 case AArch64::MOVPRFX_ZPmZ_H: in CreateFromInst()
103 case AArch64::MOVPRFX_ZPmZ_S: in CreateFromInst()
104 case AArch64::MOVPRFX_ZPmZ_D: in CreateFromInst()
107 Prefix.ElementSize = TSFlags & AArch64::ElementSizeMask; in CreateFromInst()
108 assert(Prefix.ElementSize != AArch64::ElementSizeNone && in CreateFromInst()
113 case AArch64::MOVPRFX_ZPzZ_B: in CreateFromInst()
114 case AArch64::MOVPRFX_ZPzZ_H: in CreateFromInst()
115 case AArch64::MOVPRFX_ZPzZ_S: in CreateFromInst()
[all …]

1234567