Searched refs:v9a (Results 1 – 7 of 7) sorted by relevance
61 #define v9a (MASK_V9A | MASK_V9B) macro836 { "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr…837 { "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */838 { "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic…839 { "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */840 { "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr…841 { "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */842 { "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr…843 { "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */844 { "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set…[all …]
138 * sparc-opc.c: Add wr & rd for v9a asr's.139 * sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's.472 * sparc-opc.c: The fcmp v9a instructions take an integer register2095 (v6,v7,v8,sparclite,v9,v9a): Redefine.2192 (sparc_opcodes): Add v9a shutdown insn.2197 If DISASM_RAW_INSN, print insn in hex. Handle v9a as opcode2203 * sparc-opc.c (architecture_pname): Add v9a.
229 v8plusa, v9, v9a, v9b, v9_64}; enumerator
1758 * sparc.h: Add '_' and '/' for v9a asr's.2354 * sparc.h (enum sparc_architecture): Add v9a.
347 (sparc_ip): Handle v9a asr's.393 (sparc_arch_table): Always include v9, v9a. New entry v9-64.
10237 msgid ": unrecognizable v9a or v9b ancillary state register"10246 msgid ": unrecognizable v9a ancillary state register"
6340 Add v9a support.