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Searched refs:v32i8 (Results 1 – 17 of 17) sorted by relevance

/freebsd-9-stable/contrib/llvm/include/llvm/CodeGen/
DValueTypes.h75 v32i8 = 24, // 32 x i8 enumerator
224 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
278 case v32i8: in getVectorElementType()
316 case v32i8: in getVectorNumElements()
415 case v32i8: in getSizeInBits()
518 if (NumElements == 32) return MVT::v32i8; in getVectorVT()
DValueTypes.td47 def v32i8 : ValueType<256, 24>; // 32 x i8 vector value
/freebsd-9-stable/contrib/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp194 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence. in getArithmeticInstrCost()
197 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized. in getArithmeticInstrCost()
200 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized. in getArithmeticInstrCost()
205 { ISD::SDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
209 { ISD::UDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
486 { ISD::SETCC, MVT::v32i8, 4 }, in getCmpSelInstrCost()
493 { ISD::SETCC, MVT::v32i8, 1 }, in getCmpSelInstrCost()
DX86CallingConv.td49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
249 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
271 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
295 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
412 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
420 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
DX86InstrSSE.td297 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
298 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
314 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
374 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
379 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
381 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
382 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
383 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
384 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
[all …]
DX86InstrAVX512.td55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
DX86RegisterInfo.td438 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
463 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
DX86ISelLowering.cpp1117 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); in resetOperationActions()
1167 setOperationAction(ISD::SRL, MVT::v32i8, Custom); in resetOperationActions()
1170 setOperationAction(ISD::SHL, MVT::v32i8, Custom); in resetOperationActions()
1173 setOperationAction(ISD::SRA, MVT::v32i8, Custom); in resetOperationActions()
1177 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); in resetOperationActions()
1217 setOperationAction(ISD::ADD, MVT::v32i8, Legal); in resetOperationActions()
1222 setOperationAction(ISD::SUB, MVT::v32i8, Legal); in resetOperationActions()
1229 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); in resetOperationActions()
1236 setOperationAction(ISD::ADD, MVT::v32i8, Custom); in resetOperationActions()
1241 setOperationAction(ISD::SUB, MVT::v32i8, Custom); in resetOperationActions()
[all …]
DX86InstrFragmentsSIMD.td457 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
/freebsd-9-stable/contrib/llvm/lib/Target/R600/
DSIInstructions.td1440 (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm),
1445 (name vt:$addr, v32i8:$rsrc, i128:$sampler, imm),
1450 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_RECT),
1455 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_ARRAY),
1461 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW),
1467 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW_ARRAY),
1520 (name addr_type:$addr, v32i8:$rsrc, imm),
1525 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
1530 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
1535 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
[all …]
DSIRegisterInfo.td164 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
179 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
DSIInstrInfo.td49 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
DSIISelLowering.cpp37 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
/freebsd-9-stable/contrib/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp78 DecodePALIGNRMask(MVT::v32i8, in EmitAnyX86InstComments()
160 DecodeUNPCKHMask(MVT::v32i8, ShuffleMask); in EmitAnyX86InstComments()
233 DecodeUNPCKLMask(MVT::v32i8, ShuffleMask); in EmitAnyX86InstComments()
/freebsd-9-stable/contrib/llvm/lib/IR/
DValueTypes.cpp142 case MVT::v32i8: return "v32i8"; in getEVTString()
210 case MVT::v32i8: return VectorType::get(Type::getInt8Ty(Context), 32); in getTypeForEVT()
/freebsd-9-stable/contrib/llvm/utils/TableGen/
DCodeGenTarget.cpp83 case MVT::v32i8: return "MVT::v32i8"; in getEnumName()
/freebsd-9-stable/contrib/llvm/include/llvm/IR/
DIntrinsics.td148 def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8