| /freebsd-9-stable/contrib/llvm/lib/Target/Mips/ |
| D | MipsDSPInstrInfo.td | 1283 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1285 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1288 def : DSPPat<(v2i16 (load addr:$a)),
1289 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1292 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1302 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1303 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1304 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1305 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1306 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
[all …]
|
| D | MipsRegisterInfo.td | 270 def DSPR : GPR32Class<[v4i8, v2i16]>;
373 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
|
| D | MipsSEISelLowering.cpp | 61 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; in MipsSETargetLowering()
85 setOperationAction(ISD::MUL, MVT::v2i16, Legal); in MipsSETargetLowering()
777 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) in performSHLCombine()
834 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2())) in performSRACombine()
846 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8)) in performSRLCombine()
853 bool IsV216 = (Ty == MVT::v2i16); in isLegalDSPCondCode()
873 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) in performSETCCCombine()
925 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) { in performVSELECTCombine()
|
| /freebsd-9-stable/contrib/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 78 v2i16 = 27, // 2 x i16 enumerator
203 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 || in is32BitVector()
281 case v2i16: in getVectorElementType()
344 case v2i16: in getVectorNumElements()
389 case v2i16: in getSizeInBits()
523 if (NumElements == 2) return MVT::v2i16; in getVectorVT()
|
| D | ValueTypes.td | 50 def v2i16 : ValueType<32 , 27>; // 2 x i16 vector value
|
| /freebsd-9-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 243 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
244 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
275 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost()
276 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost()
|
| D | ARMInstrNEON.td | 6179 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
6183 // v2i8 -> v2i16 -> v2i32
6185 // v2i16 -> v2i32 -> v2i64
6188 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
|
| D | ARMISelLowering.cpp | 604 MVT::v4i16, MVT::v2i16, in ARMTargetLowering()
5577 case MVT::v2i16: in getExtensionTo64Bits()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 51 (int)MVT::v2i16, in InitAMDILLowering()
76 (int)MVT::v2i16, in InitAMDILLowering()
192 setOperationAction(ISD::UDIV, MVT::v2i16, Expand); in InitAMDILLowering()
565 if (OVT == MVT::v2i16) { in LowerSREM16()
|
| D | AMDGPUISelLowering.cpp | 93 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); in AMDGPUTargetLowering()
129 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand); in AMDGPUTargetLowering()
130 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand); in AMDGPUTargetLowering()
131 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand); in AMDGPUTargetLowering()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 25 // Extract v2i16
30 (v2i16 V2I16Regs:$src), imm:$c))],
125 // Insert v2i16
790 def : Pat<(v2i16 (vec_shuf:$op V2I16Regs:$src1, V2I16Regs:$src2)),
884 def : Pat<(v2i16 (extract_subvec V4I16Regs:$src, 0)),
887 def : Pat<(v2i16 (extract_subvec V4I16Regs:$src, 2)),
1268 // v2i16 -> i32
1294 // i32 -> v2i16
1307 // v4i8 -> v2i16
1308 def : Pat<(v2i16 (bitconvert V4I8Regs:$s)),
[all …]
|
| D | NVPTXISelLowering.cpp | 58 case MVT::v2i16: in IsPTXVectorType()
1243 case MVT::v2i16: in LowerSTOREVector()
2060 case MVT::v2i16: in ReplaceLoadVector()
|
| /freebsd-9-stable/contrib/llvm/lib/IR/ |
| D | ValueTypes.cpp | 145 case MVT::v2i16: return "v2i16"; in getEVTString()
213 case MVT::v2i16: return VectorType::get(Type::getInt16Ty(Context), 2); in getTypeForEVT()
|
| /freebsd-9-stable/contrib/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 86 case MVT::v2i16: return "MVT::v2i16"; in getEnumName()
|
| /freebsd-9-stable/contrib/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConv.td | 63 CCIfType<[v1i32, v4i8, v2i16, v1f32], CCBitConvertToType<f32>>,
|
| /freebsd-9-stable/contrib/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 152 def llvm_v2i16_ty : LLVMType<v2i16>; // 2 x i16
|
| D | IntrinsicsMips.td | 16 def mips_v2q15_ty: LLVMType<v2i16>;
|