Home
last modified time | relevance | path

Searched refs:v2f32 (Results 1 – 25 of 26) sorted by relevance

12

/freebsd-9-stable/contrib/llvm/lib/Target/ARM/
DARMCallingConv.td27 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
46 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
60 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
72 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
88 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
138 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
148 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
166 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
178 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
DARMTargetTransformInfo.cpp191 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
241 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
242 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
243 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
244 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
245 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
246 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
453 { ISD::VECTOR_SHUFFLE, MVT::v2f32, 1 }, in getShuffleCost()
DARMInstrNEON.td1036 def : Pat<(vector_insert (v2f32 DPR:$src),
1313 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1986 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
3145 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3148 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3991 v2f32, v2f32, fadd, 1>;
4046 v2f32, v2f32, fmul, 1>;
4050 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
4052 v2f32, fmul>;
4069 (v2f32 (EXTRACT_SUBREG QPR:$src2,
[all …]
DARMRegisterInfo.td284 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
293 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
298 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
DARMISelLowering.cpp460 addDRTypeForNEON(MVT::v2f32); in ARMTargetLowering()
529 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand); in ARMTargetLowering()
530 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
531 setOperationAction(ISD::FCOS, MVT::v2f32, Expand); in ARMTargetLowering()
532 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand); in ARMTargetLowering()
533 setOperationAction(ISD::FPOW, MVT::v2f32, Expand); in ARMTargetLowering()
534 setOperationAction(ISD::FLOG, MVT::v2f32, Expand); in ARMTargetLowering()
535 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand); in ARMTargetLowering()
536 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand); in ARMTargetLowering()
537 setOperationAction(ISD::FEXP, MVT::v2f32, Expand); in ARMTargetLowering()
[all …]
DARMISelDAGToDAG.cpp1801 case MVT::v2f32: in SelectVLD()
1937 case MVT::v2f32: in SelectVST()
2099 case MVT::v2f32: in SelectVLDSTLane()
2211 case MVT::v2f32: in SelectVLDDup()
2758 case MVT::v2f32: in Select()
2778 case MVT::v2f32: in Select()
2798 case MVT::v2f32: in Select()
/freebsd-9-stable/contrib/llvm/include/llvm/CodeGen/
DValueTypes.h101 v2f32 = 46, // 2 x f32 enumerator
211 SimpleTy == MVT::v1f64 || SimpleTy == MVT::v2f32); in is64BitVector()
300 case v2f32: in getVectorElementType()
348 case v2f32: in getVectorNumElements()
402 case v2f32: in getSizeInBits()
550 if (NumElements == 2) return MVT::v2f32; in getVectorVT()
DValueTypes.td70 def v2f32 : ValueType<64 , 46>; // 2 x f32 vector value
/freebsd-9-stable/contrib/llvm/lib/Target/AArch64/
DAArch64InstrNEON.td182 (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
211 v2f32, v4f32, v2f64, 1>;
217 v2f32, v4f32, v2f64, 0>;
223 v2f32, v4f32, v2f64, 1>;
288 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s", VPR64, v2f32,
295 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s", VPR64, v2f32,
305 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
312 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
322 v2f32, v4f32, v2f64, 0>;
471 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
[all …]
DAArch64RegisterInfo.td163 [f64, v2f32, v2i32, v4i16, v8i8, v1i64, v1f64],
171 [f64, v2f32, v2i32, v4i16, v8i8, v1i64, v1f64],
DAArch64ISelLowering.cpp69 addRegisterClass(MVT::v2f32, &AArch64::FPR64RegClass); in AArch64TargetLowering()
296 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); in AArch64TargetLowering()
309 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Custom); in AArch64TargetLowering()
333 setOperationAction(ISD::SETCC, MVT::v2f32, Custom); in AArch64TargetLowering()
338 setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal); in AArch64TargetLowering()
343 setOperationAction(ISD::FCEIL, MVT::v2f32, Legal); in AArch64TargetLowering()
348 setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal); in AArch64TargetLowering()
353 setOperationAction(ISD::FRINT, MVT::v2f32, Legal); in AArch64TargetLowering()
358 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Legal); in AArch64TargetLowering()
363 setOperationAction(ISD::FROUND, MVT::v2f32, Legal); in AArch64TargetLowering()
[all …]
DAArch64CallingConv.td64 CCIfType<[v8i8, v4i16, v2i32, v2f32, v1i64, v1f64], CCBitConvertToType<f64>>,
/freebsd-9-stable/contrib/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp71 setOperationAction(ISD::STORE, MVT::v2f32, Promote); in AMDGPUTargetLowering()
72 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
103 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
104 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
121 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
138 setOperationAction(ISD::FNEG, MVT::v2f32, Expand); in AMDGPUTargetLowering()
148 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand); in AMDGPUTargetLowering()
178 MVT::v2f32, MVT::v4f32 in AMDGPUTargetLowering()
DAMDILISelLowering.cpp55 (int)MVT::v2f32, in InitAMDILLowering()
80 (int)MVT::v2f32, in InitAMDILLowering()
404 FLTTY = MVT::v2f32; in LowerSDIV24()
DSIRegisterInfo.td171 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>;
DR600RegisterInfo.td209 def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,
DR600Instructions.td2364 def : Extract_Element <f32, v2f32, 0, sub0>;
2365 def : Extract_Element <f32, v2f32, 1, sub1>;
2367 def : Insert_Element <f32, v2f32, 0, sub0>;
2368 def : Insert_Element <f32, v2f32, 1, sub1>;
2380 def : BitConvert <v2f32, v2i32, R600_Reg64>;
2381 def : BitConvert <v2i32, v2f32, R600_Reg64>;
DSIInstructions.td1584 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1587 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1649 def : BitConvert <v2f32, v2i32, VReg_64>;
1650 def : BitConvert <v2i32, v2f32, VReg_64>;
2100 defm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>;
DR600ISelLowering.cpp36 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
85 setOperationAction(ISD::SELECT, MVT::v2f32, Expand); in R600TargetLowering()
618 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32, in LowerOperation()
DSIISelLowering.cpp45 addRegisterClass(MVT::v2f32, &AMDGPU::VSrc_64RegClass); in SITargetLowering()
/freebsd-9-stable/contrib/llvm/lib/Target/NVPTX/
DNVPTXVector.td65 // Extract v2f32
70 (v2f32 V2F32Regs:$src), imm:$c))],
152 // Insert v2f32
768 def : Pat<(v2f32 (vec_shuf:$op V2F32Regs:$src1, V2F32Regs:$src2)),
872 def : Pat<(v2f32 (extract_subvec V4F32Regs:$src, 0)),
875 def : Pat<(v2f32 (extract_subvec V4F32Regs:$src, 2)),
1339 // f64 -> v2f32
1348 // v2f32 -> f64
1387 // i64 -> v2f32
1388 def : Pat<(v2f32 (bitconvert Int64Regs:$s)),
[all …]
DNVPTXISelLowering.cpp63 case MVT::v2f32: in IsPTXVectorType()
1246 case MVT::v2f32: in LowerSTOREVector()
2063 case MVT::v2f32: in ReplaceLoadVector()
/freebsd-9-stable/contrib/llvm/lib/IR/
DValueTypes.cpp161 case MVT::v2f32: return "v2f32"; in getEVTString()
232 case MVT::v2f32: return VectorType::get(Type::getFloatTy(Context), 2); in getTypeForEVT()
/freebsd-9-stable/contrib/llvm/utils/TableGen/
DCodeGenTarget.cpp105 case MVT::v2f32: return "MVT::v2f32"; in getEnumName()
/freebsd-9-stable/contrib/llvm/include/llvm/IR/
DIntrinsics.td173 def llvm_v2f32_ty : LLVMType<v2f32>; // 2 x float

12